Rev. 5.00, 09/03, page 562 of 760
Bits 6 to 3—Ir Clock Select Bits (ICK3 to ICK0)
Bit 2—Output Pulse Width Select (PSEL): PSEL selects an IrDA output pulse width that is 3/16
of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate.
The Ir cl ock select bits should be s et properly to fix the output pulse width at 3/16 of the bit length
for 115 kbps by setting the PSEL bit to 1.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Description
ICK3 ICK2 ICK1 ICK0 PSEL Puls e width: 3/16 of 115 kbps bit length
ICK3 ICK2 ICK1 ICK0 1
Don’t
care Don’t
care Don’t
care Don’t
care 0 Pulse width: 3/16 of bit length
It is neces sary to generate a fixed clock pulse, IRCLK, by dividing the Pφ clock by 1/2N + 2 (with
the value of N determined by the setting of ICK3–ICK0).
Example:
Pφ clock: 14.74 56 MHz
IRCLK: 921.6 kHz (fixed)
N: Setting of ICK3–ICK0 (0 ≤ N ≤ 15)
− 1 ≥ 7 N ≥ Pφ
2XIRCLK
Accordingly, N is 7.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal baud rate generator clock
source. Pφ, Pφ/4, Pφ/16, or Pφ/64 can be selected by sett i ng the CKS1 and CKS0 bits.
Refer to section 14.2. 9, Bit Rate Register (SCBRR), for the relat ionshi p between the clock source,
the bit rate register set value, and the baud rate.
Bit 1: CKS1 Bit 0: CKS0 Description
00Pφ clock (Initial value)
01Pφ/4 clock
10Pφ/16
11Pφ/64
Note: Pφ: Peripheral clock