Renesas SH7709S

Rev. 5.00, 09/03, page 19 of 760

Section 2 CPU

2.1 Register Configuration

2.1.1 Privileged Mode and Banks

Processor M odes: There are two processor modes: user mode and privileged mode. The

SH7709S normally operates in user mode, and enters privileged mode when an except i on occurs

or an interrupt is accepted. There are three kinds of registers—general registers, system registers,

and control registers—and the registers that can be accessed differ in the two processor modes.

General Registers: There are 16 general registers, designated R0 t o R 15. General registers R0 to

R7 are banked registers which are switched by a processor mode change. In privileged mode, the

general registers, and which set is accessed only through the load control register (LDC) and store

control register (STC) instructions.

When the RB bit is 1, the 16 registers comprising BANK1 general registers R0_BANK1–

R7_BANK1 and non-banked general registers R8–R15 function as the general register set, with

the 8 registers comprising BANK0 general registers R0_BANK0–R7_BANK0 accessed only by

the LDC/STC instructio ns.

When the RB bit is 0, BANK0 general registers R0_BANK0–R7_BANK0 and nonbanked general

registe r s R8– R1 5 funct io n as the gene ra l regis t er set, with BAN K1 gener al re gi ster s R0 _B ANK 1–

R7_BANK1 accessed only by the LDC/STC instructi ons. In user mode, the 16 registers

comprising bank 0 general registers R0_BANK0–R7_B ANK0 and no n-ba nked registers R8– R15

can be accessed as general registers R0–R15, and bank 1 general registers R0_BANK1–

R7_BANK1 cannot be accessed.

Control Registers: Control registers comprise the globa l base register (GBR) and status register

(SR) which can be accessed in both processor modes, and the saved status register (SSR), saved

program counter (SPC), and vec tor base register (VBR) wh i c h can only be accessed in privileged

mode. So me bits of the status re gister (such as the R B bit) can only be accessed in privileged

mode.

Syste m Registers: Syste m registers comprise the multiply and accumulate registers

(MACL/MACH), the procedure registe r (PR), and the prog ram count er (PC). A ccess to these

registers does not depend on the processor mode.

The register configuration in each mode is shown in figures 2.1 and 2.2.

Switching between user mode and privileged mode is controlled by the processor mode bit (MD)

in the status register.