Rev. 5.00, 09/03, page 664 of 760
23.3.1 Clock Timing
Table 23.5 Clock Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
EXTAL clock input frequency (clock mode 0) fEX 25 66.67 MHz 23.1
EXTAL clock input cycle time (clock mode 0) tEXcyc 15 40 ns
EXTAL clock input frequency (clock mode 1) fEX 6.25 16.67 MHz
EXTAL clock input cycle time (clock mode 2) tEXcyc 60 160 ns
EXTAL clock input low pulse width tEXL 1.5 — ns
EXTAL clock input high pulse width tEXH 1.5 — ns
EXTAL clock input rise time tEXR —6 ns
EXTAL clock input fall time tEXF —6 ns
CKIO clock input frequency fCKI 20 66 MHz 23.2
CKIO clock input cycle time tCKIcyc 15.2 40 ns
CKIO clock input low pulse width tCKIL 1.5 — ns
CKIO clock input high pulse width tCKIH 1.5 — ns
CKIO clock input rise time tCKIR —6 ns
CKIO clock input fall time tCKIF —6 ns
CKIO clock output frequency fOP 25 66 MHz 23.3
CKIO clock output cycle time tcyc 15.2 40 ns
CKIO clock out put low pulse width tCKOL 3—ns
CKIO clock output hi gh pulse width tCKOH 3—ns
CKIO clock output rise time tCKOR —5 ns
CKIO clock output fall time tCKOF —5 ns
CKIO2 clock o utput delay time tCK2D –3 3 ns
CKIO2 clock output rise ti me tCK20R —7 ns
CKIO2 clock output fall time tCK20F —7 ns
Power-on oscillation settling time tOSC1 10 — ms 23.4
RESETP setup time tRESPS 20 — ns 23.4, 23.5
RESETM setup time tRESMS 6—ns
RESETP assert time tRESPW 20 — tcyc
RESETM assert time tRESMW 20 — tcyc
Standby retu rn o scillation settling time 1 tOSC2 10 — ms 23.5
Standby retu rn o scillation settling time 2 tOSC3 10 — ms 23.6
Standby retu rn o scillation settling time 3 tOSC4 11 — ms 23.7
PLL synchronization settling time 1
(standby canceled) tPLL1 100 — µs 23.8, 23.9
PLL synchronization settling time 2
(multipl ication rete modified) tPLL2 100 — µs 23.10
IRQ/IRL interrupt determination time
(RTC used and standby mode) tIRLSTB 100 — µs 23.9