Rev. 5.00, 09/03, page 670 of 760
23.3.2 Control S ignal Timing
Table 23.6 Control Signal Timing
Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
RESETP pulse width tRESPW 20 *2— tcyc 23.11,
RESETP setup time*1tRESPS 20 — ns 23.12
RESETP hold time tRESPH 4—ns
RESETM pulse width tRESMW 20 *3—tcyc
RESETM setup time tRESMS 6—ns
RESETM hold time tRESMH 34 — ns
BREQ setup time tBREQS 6 — ns 23.14
BREQ hold time tBREQH 4—ns
NMI setup time *1tNMIS 10 — ns 23.12
NMI hold time tNMIH 4—ns
IRQ5–IRQ0 setup time *1tIRQS 10 — ns
IRQ5–IRQ0 hold time tIRQH 4—ns
IRQOUT delay time tIRQOD — 10 ns 23.13
BACK delay time tBACKD — 10 ns 23.14,
STATUS1, STATUS0 delay time tSTD — 10 ns 23.15
Bus tri-state delay time 1 tBOFF1 015ns
Bus tri-state delay time 2 tBOFF2 015ns
Bus buffer-on time 1 tBON1 015ns
Bus buffer-on time 2 tBON2 015ns
Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock fall when the setup shown is used. When the setup cannot be used, detecti on
can be delayed until the n ext clock falls.
2. In the standby mode, tRESPW = tOSC1 (100 µs) when XTAL oscillation is continued and
tRESPW = tOSC2 (10 ms) when XTAL oscillation is off. In the sleep mode, tRESPW = tPLL1
(100 µs).
When the clock mu ltip lic ati on ratio is cha nged, tRESPW = tPLL1 (100 µs).
3. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept
low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).