Rev. 5.00, 09/03, page 680 of 760
CKIO
A25 to A4
A3 to A0
CSn
RD/WR
RD
D31 to D0
BS
DACKn
WAIT
T1TwTwTB2 TB1 T2
TBw
tAD tAD
tCSD1 tCSD2
tRWD
tRWH
tRDH1
tAH
tAH
tRWD
tRSD
tRSD1 tAH
tAD
tBSD
tBSD
tWTS tWTH
tWTS tWTH
tWTS tWTH
tWTS tWTH
tBSD tBSD
tRDS1
tRDH1
tRSD
tDAKD1 tDAKD2
tRDH1
tRWH
tRSD1
tRDS
Note: In the write cycle, the basic bus cycle is performed.
Figure 23.21 Burst ROM Bus Cycl e (External Wait, WAITSEL = 1)