Rev. 5.00, 09/03, page 686 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tr Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc)
(High)
D31 to D0
tAD
Row address
Row
address
Write A
command
Row
address
Column
address
tAD tAD
tAD tAD
tAD
tAD
tCSD1
tRWD tRWD
tAD
tAD
tAD
tCSD1
tRWD
tRASD2 tRASD2
tDQMD
tWDD2
tBSD
tCASD2
tDQMD
tWDH2
tBSD
tCASD2
tDAKD1 tDAKD1
DACKn
Figure 23.27 Synchronous DRAM Write Bus Cycle (RCD =
==
= 2, TPC =
==
= 1, TRWL = 1)