Rev. 5.00, 09/03, page 692 of 760
CKIO
A12 or A10
RD/WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tp Tpw Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3
D31 to D0
tAD
tAD
tCSD3
tCSD3
tRWD
tRWD tRWD
tRASD2 tRASD2 tRASD2 tRASD2
tDQMD tDQMD tDQMD
tBSD
tBSD
(High)
tAD tAD tAD
tAD tAD tAD
tRDS2 tRDH2 tRDS2 tRDH2
tAD
Td4
Row address
Read command
Column address
tCASD2 tCASD2
Row
address
Row
address
tDAKD1 tDAKD1
DACKn
Figure 23.33 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1)