Rev. 5.00, 09/03, page 690 of 760
A25 to A16
(High)
tAD
tAD
tAD
tCASD2
tCSD3
tRWD
tDQMD
tBSD
tRDH2
tRDS2
tRDH2
tRDS2
tBSD
tRASD2
tCASD2
tDQMD
tRWD
tCSD3
tAD
tAD
tAD
Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4
CKIO
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
CKE
Row address
DACKn
tDAKD1 tDAKD1
Column address
Read command
Figure 23.31 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Same Row Address, CAS Latency = 2)