Rev. 5.00, 09/03, page 699 of 760
23.3.7 PCMCIA Timing
Tpcm1 Tpcm2
CKIO
A25 to A0
CExx
RD/WR
RD
D15 to D0
WE1
D15 to D0
BS
DACKn
tAD tAD
tCSD1 tCSD1
tRWD
tRSD tRSD
tRWD
tDAKD1 tDAKD1
tWED
tWDD1
tWED
tRDS1
tRDH1
tBSD
tBSD
tWDH4
tWDH1
(read)
(read)
(write)
(write)
Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)