Rev. 5.00, 09/03, page 702 of 760
tRDS1
tRSD
CKIO
Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w
A25 to A4
A3 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
Note: Even though burst mode is set, the write cycle operation is the same as in normal mode.
BS
DACKn
WAIT
tAD tAD
tCSD1
tRWD
tCSD1
tDAKD1
tRWD
tAD tAD
tAD
tRSD
tRSD tRSD
tDAKD1
tBSD
tBSD tBSD tBSD
tRDH1 tRDH1
tRDS1
tWTS tWTH
tWTS
tWTS tWTH
tWTH
Figure 23.43 PCMCIA Memory Bus Cycle
(Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1)