Rev. 5.00, 09/03, page 706 of 760
23.3.8 Peripheral Module Signal Timing
Table 23.8 Peripheral Module Signal Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module Item Symbol Min Max Unit Figure
Timer input setup time tTCLKS 15 —ns 23.47TMU,
RTC Timer clock input setup time tTCKS 15 —23.48
Edge specification tTCKWH 1.5 —PcycTimer clock
pulse width Both edge specification tTCKWL 2.5 —
Oscillati on sett ling time tROSC 3 — s 23.49
SCI Asynchronization tSCYC 4 — Pcyc*23.50Input clock
cycle Clock sy nchroniz ation 6 —23.51
Input clock rise time tSCKR —1.5 23.50
Input clock fall time tSCKF —1.5
Input clock pulse width tSCKW 0.4 0.6 tscyc
Transmission data delay time tTXD —100 ns 23.51
Receive data setup time (clock
synchronization) tRXS 100 —
Receive data hold time (clock
synchronization) tRXH 100 —
RTS delay time tRTSD —100
CTS setup time (clock synchronization) tCTSS 100 —
CTS hold time (clock synchronization) tCTSH 100 —
Port Output data delay time tPORTD —17 ns 23.52
Input data setup time tPORTS1 15 —
Input data hold time tPORTH1 8 —
Input data setup time tPORTS2 tcyc +
15 —
Input data hold time tPORTH2 8 —
Input data setup time tPORTS3 3 × tcyc
+ 15 —
Input data hold time tPORTH3 8 —
DMAC DREQ setup time tDRQS 6 — ns 23.53
DREQ hold time tDREQH 4 —
DRAK delay time tDRAKD —10 23.54
Note: * Pcyc is the P clock cycle.