xv
3.4.14 Typematic Delay (msec)............................................... 35
3.4.15 Security Option............................................................. 36
3.4.16 APIC Mode................................................................... 36
3.4.17 MPS Version Control For OS....................................... 36
3.4.18 OS Select For DRAM > 64MB.................................... 36
3.4.19 Report No FDD For WIN 95........................................ 36
3.4.20 Small Logo(EPA) Show............................................... 36
3.5 Advanced Chipset Features.............................................37
Figure 3.4:Advanced chipset features screen ............... 37
3.5.1 DRAM Timing Selectable............................................ 37
3.5.2 CAS Latency Time....................................................... 37
3.5.3 Active to Precharge Delay............................................ 37
3.5.4 DRAM RAS# to CAS# Delay..................................... 38
3.5.5 DRAM RAS# Precharge...............................................38
3.5.6 DRAM Data Integrity Mode.........................................38
3.5.7 System BIOS Cacheable............................................... 38
3.5.8 Video Bios Cacheable...................................................38
3.5.9 Memory Hole At 15M-16M......................................... 38
3.5.10 Delayed Transaction..................................................... 38
3.5.11 Delay Prior to Thermal................................................. 38
3.5.12 AGP Aperture Size (MB)............................................. 39
3.5.13 Init Display First.......................................................... 39
3.5.14 On-Chip VGA............................................................... 39
3.5.15 On-Chip Frame Buffer Size.......................................... 39
3.5.16 Boot display.................................................................. 39
3.5.17 Panel Number.............................................. .................39
3.6 Integrated Peripherals......................................................40
Figure 3.5:Integrated peripherals.................................. 40
3.7 On-chip IDE Device........................................................ 40
Figure 3.6:On-Chip IDE Device................................... 40
3.7.1 IDE DMA transfer access............................................. 40
3.7.2 On-Chip IDE Device.................................................... 41
3.7.3 On-Chip Serial ATA..................................................... 41
3.7.4 Serial ATA Port0/Port1 Mode...................................... 41
3.7.5 IDE HDD Block Mode................................................. 41
3.8 Onboard Device Menu....................................................41
Figure 3.7:Onboard Device...........................................41
3.8.1 USB Controller............................................................. 42
3.8.2 USB 2.0 Controller....................................................... 42
3.8.3 USB Keyboard/Mouse Support....................................42
3.8.4 AC97 Audio.................................................................. 42
3.8.5 On-board LAN1 Control...............................................42
3.8.6 On-board LAN2 Control...............................................42
3.9 SuperIO Device...............................................................42
Figure 3.8:SuperIO Device..................... ......................42