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SMSC USB2512 4.6.2External Hardware RESET_N, 4.6.2.1RESET_N for Strapping Option Configuration, MIN, TYP, MAX, NAME, UNITS, DESCRIPTION

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USB 2.0 High-Speed 2-Port Hub Controller

Datasheet

4.6.2External Hardware RESET_N

A valid hardware reset is defined as assertion of RESET_N for a minimum of 1us after all power supplies are within operating range. While reset is asserted, the Hub (and its associated external circuitry) consumes less than 500μA of current from the upstream USB power source.

Assertion of RESET_N (external pin) causes the following:

1.All downstream ports are disabled, and PRTPWR power to downstream devices is removed.

2.The PHYs are disabled, and the differential pairs will be in a high-impedance state.

3.All transactions immediately terminate; no states are saved.

4.All internal registers return to the default state (in most cases, 00(h)).

5.The external crystal oscillator is halted.

6.The PLL is halted.

The Hub is “operational” 500μs after RESET_N is negated.

Once operational, the Hub immediately reads OEM-specific data from the external EEPROM (if the SMBus option is not disabled).

4.6.2.1RESET_N for Strapping Option Configuration

	Hardware		Drive Strap	Attach			Start
		Read Strap	Outputs to		USB Reset		completion
	reset			USB		Idle
		Options	inactive		recovery		request
	asserted			Upstream
			levels				response

t1

t5

t6

t7

t8

t2

RESET_N

t3

VSS

t4

Strap Pins

Don’t Care

Valid

Don’t Care

Driven by Hub if strap is an output.

VSS

Figure 4.3 Reset_N Timing for Default/Strap Option Mode

Table 4.3 Reset_N Timing for Default/Strap Option Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNITS

t1

RESET_N Asserted.

1

μsec

t2

Strap Setup Time

16.7

nsec

t3

Strap Hold Time.

16.7

1400

nsec

t4

hub outputs driven to inactive logic states

1.5

2

μsec

t5

USB Attach (See Note).

100

msec

t6

Host acknowledges attach and signals USB

100

msec

Reset.

Revision 1.92 (11-28-07)	28	SMSC USB2512
	DATASHEET

Contents

USB2512 USB 2.0 High-Speed 2-PortHub Controller PRODUCT FEATURES General Description ORDER NUMBER(S): USB2512-AEZGFOR 36 PIN, QFN LEAD-FREEROHS COMPLIANT PACKAGE Table of Contents Chapter List of Figures List of Tables Chapter 1 Pin Configuration Chapter 2 Block Diagram Chapter 3 Pin Descriptions 3.1PIN Descriptions Table 3.1 USB2512 Pin Descriptions (continued) SERIAL PORT INTERFACE MISC Table 3.2 SMBus or EEPROM Interface Behavior CFG_SEL1 CFG_SEL0 SMBUS OR EEPROM INTERFACE BEHAVIOR Table 3.2 SMBus or EEPROM Interface Behavior (continued) Table 3.3 USB2512 Power, Ground, and No Connect PACKAGE SYMBOL 36-QFNEMB FUNCTION 3.2Buffer Type Descriptions Chapter 4 Configuration Options 4.12-PortHub 4.1.1Hub Configuration Options 4.1.1.1Power Switching Polarity 4.1.2VBus Detect 4.2.1.1Register 00h: Vendor ID (LSB) 4.2.1.2Register 01h: Vendor ID (MSB) 4.2.1.3Register 02h: Product ID (LSB) 4.2.1.4Register 03h: Product ID (MSB) 4.2.1.5Register 04h: Device ID (LSB) 4.2.1.6Register 05h: Device ID (MSB) 4.2.1.7Register 06h: CONFIG_BYTE_1 4.2.1.8Register 07h: Configuration Data Byte 4.2.1.9Register 08h: Configuration Data Byte 4.2.1.10Register 09h: Non-RemovableDevice Register 0Ah: Port Disable For Self Powered Operation 4.2.1.12Register 0Bh: Port Disable For Bus Powered Operation 4.2.1.13Register 0Ch: Max Power For Self Powered Operation 4.2.1.14Register 0Dh: Max Power For Bus Powered Operation 4.2.1.15Register 0Eh: Hub Controller Max Current For Self Powered Operation 4.2.1.16Register 0Fh: Hub Controller Max Current For Bus Powered Operation Register 10h: Power-OnTime 4.2.1.18Register F6h: Boost_Up 4.2.1.19Register F8h: Boost_2:0 4.2.1.20Register FAh: Port Swap Register FBh: Port Remap 4.2.1.22Register FFh: Status/Command 4.2.2 I2C EEPROM 4.2.2.1Implementation Characteristics 4.2.2.2Pull-UpResistor 4.2.2.3I2C EEPROM Slave Address 4.2.3In-CircuitEEPROM Programming 4.3SMBus Slave Interface 4.3.1Bus Protocols 4.3.1.1Block Read/Write 4.3.2Invalid Protocol Response Behavior 4.3.3General Call Address Response 4.3.4Slave Device Time-Out 4.3.5Stretching the SCLK Signal 4.3.6SMBus Timing 4.4Default Configuration Option: 4.5Default Strapping Options: 4.6Reset 4.6.1Internal POR Hardware Reset 4.6.2External Hardware RESET_N 4.6.2.1RESET_N for Strapping Option Configuration 4.6.2.2RESET_N for EEPROM Configuration 4.6.2.3RESET_N for SMBus Slave Configuration 4.6.3USB Bus Reset Page Chapter 5 DC Parameters 5.1Maximum Guaranteed Ratings 5.2Recommended Operating Conditions Table DC Electrical Characteristics I, IS Type Input Buffer Input Buffer with Pull-Up (IPU) Table 5.1 DC Electrical Characteristics (continued) CAPACITANCE TA = 25°C; fc = 1MHz; VDD18, VDDPLL Chapter 6 AC Specifications 6.1Oscillator/Clock 6.1.1SMBus Interface: 6.1.2I2C EEPROM: 6.1.3USB Chapter 7 Package Outline