General Description
The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 56 pin QFN.
The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary technology results in low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY can be configured for either an
All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection of DP and DM lines is provided for USB compliance.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY
Block Diagram
DATABUS16_8
RESET
SUSPENDN
XCVRSELECT
TERMSELECT
OPMODE[1:0]
LINESTATE[1:0]
CLKOUT
DATA[15:0] * TXVALID TXREADY VALIDH
RXVALID
RXACTIVE
RXERROR
VDD3 | VDD1 |
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| CONTROL |
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| TX State |
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| Serial |
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| OEB |
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| TX |
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| Conversion |
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| Encode |
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| RX |
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| Interface |
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| LOGIC |
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| UTMI |
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| VP |
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| VM |
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| Serial to |
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| Clock |
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| Parallel |
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| Conversion |
| Recovery Unit |
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| Bit Unstuff |
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| FS |
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| RX |
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| and |
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| NRZI |
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| Data |
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| MUX |
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| Decode |
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| Recovery |
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| HS |
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| Elasticity |
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| RX |
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| Buffer |
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| BIASING |
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| HS |
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| Bandgap Voltage Reference |
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| SQ |
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| Current Reference |
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| RBIAS |
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DP
DM
SMSC USB3250 | PRODUCT3 PREVIEW | Revision 1.7 |