Application Note
Interfacing to a Graphics Module with a Toshiba T6963C Controller
Introduction:
The Toshiba T6963C LCD controller is one of the most popular controllers for use in small graphics displays. For this reason it is used in a number of LCD modules from 128x128 to 240x128 pixels. This class of module is most commonly used to display a mixture of text and graphics in samall devices and instruments. It is usually interfaced directly with an embedded 8-bit microprocessor. This application note describes the use of this controller with a number of graphics modules.
The example used here is based on an 8-bit Intel I8051 microcontroller but applies to almost any micro-controller.
Functional Description:
The T6963C uses a simple 8-bit data bus to transfer all instructions and data to and from the display. After power is applied a hardware reset is issued. The controller must then be initialized with a series of commands to set up the various modes and options available to the user. Once initialized the display is ready to accept the data to be displayed. This data can be in the form of bit-mapped graphical data or text data in pseudo ASCII format. The internal character generator is biased at -20h. which means the user must subtract 20h from the ASCII code before sending it to the display.
In the bit-mapped mode each byte of data represents 8 pixels on the display. See Figure #1. Text data can be written in pseudo ASCII format and will be displayed as a 5x7 dot character. The graphical and text data are written to separate, user assigned, areas, or pages, in the display RAM within the display module. The user can then choose one of three ways to mix the text and graphics pages on the display or the text or graphics page can be displayed alone.
| 1ST BYTE | | | | | 2ND BYTE |
| | |
| D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 | |
17TH BYTE
Figure #1 Memory map of a 128x128 display
Schematic:
The 80C51 microprocessor is connected to the LCD controller chip via parallel I/O ports in this example. It could also be connected to the processor's data bus and be mapped into the processor's data memory area. See figure 2.
