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Transcend Information TS1G-32GCF133 dimensions Wear Level F5h Write Buffer E8h Write DMA CAh

Models: TS1G-32GCF133

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TS1G~32GCF133		133X CompactFlash Card

Wear Level - F5h

Write Buffer - E8h

Write DMA – CAh

Transcend Information Inc.

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Transcend Information TS1G-32GCF133 dimensions Wear Level F5h Write Buffer E8h Write DMA CAh

Contents

Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal Description133X CompactFlash Card Signal Name Dir Pin Description Inpack Iowr VCC Wait Electrical Specification TS1G~32GCF133Output Drive Type Output Drive Characteristics Signal Interface TS1G~32GCF133133X CompactFlash Card Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst TimingTS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage CardsAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBADefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hWord Default Total Data Field Type Information Identify Device EchTotal Data Field Type Information Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per TrackWords 7-8 Number of Sectors per Card Word 49 Capabilities Bit 13 Standby TimerPIO Data Transfer Cycle Timing Mode Words 10-19 Serial NumberMultiword DMA transfer Multiple Sector SettingTotal Sectors Addressable in LBA Mode Word 64 Advanced PIO transfer modes supportedWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security Status Bit 8 Security LevelValue Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Idle 97h or E3h Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register ValuesSmart Data Structure Decription