8
Circuit Description

TX APC Circuit

A portion of the power amplifier module output is
rectified by D1022 (1SS321), then delivered to APC
Q1038 (LM2904PWR), as a DC voltage which is pro-
portional to the output level of the power amplifier
module.
The APC Q1038 (LM2904PWR) is compared the rec-
tified DC voltage from the power amplifier module
and the reference voltage from the main CPU Q2002
(HD64F2266TF13), to produce a control voltage,
which regulates supply voltage to the power ampli-
fier module Q1030 (RA55H4047M), so as to main-
tain stable output power under varying antenna
loading condition.

PLL

A portion of the output from the VCO Q1009
(2SC5374) passes through the buffer amplifier
Q1010 and Q1017 (both 2SC5374), then delivered
to the programmable divider section of the PLL IC
Q1011 (MB15A01PFV1), which divided according
to the frequency dividing data that is associated with
the setting frequency input from the main CPU
Q2002 (HD64F2266TF13). It is then sent to the phase
comparator section of the PLL IC Q1011
(MB15A01PFV1).
The 11.7 MHz frequency of the reference oscillator
circuit made up of X1001 is divided by the reference
frequency divider section of Q1011 (MB15A01PFV1)
into 2340 or 1872 parts to become 5 kHz or 6.25 kHz
comparative reference frequencies, which are utilized
by the phase comparator section of Q1011
(MB15A01PFV1).
The phase comparator section of Q1011
(MB15A01PFV1) compares the phase between the
frequency-divided oscillation frequency of the VCO
circuit and comparative frequency and its output is
a pulse corresponding to the phase difference. This
pulse is integrated by the charge pump and loop fil-
ter into a control voltage (VCV) to control the oscil-
lation frequency of the VCO Q1009 (2SC5374).