What are SHARC Processors?

Common Architectural Features

SHARC processors share the following architectural features.

32/40-bit IEEE floating-point math

32-bit fixed-point multipliers with 64-bit product and 80-bit accu- mulation

No arithmetic pipeline. All computations are single cycle.

Circular buffer addressing supported in hardware

Sixteen address pointers supporting 16 circular buffers

Six nested levels of zero-overhead looping in hardware

Rich algebraic assembly language syntax

Conditional arithmetic, bit manipulation, divide and square root, bit field deposit and extract supported by instruction set

Zero-overhead background transfers at full clock rate without pro- cessor intervention

In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid unimpeded data flow to the core to main- tain the execution rate.

Figure 1-1shows a detailed block diagram of a single core SHARC 32-bit processor and the I/O processor (IOP). It illustrates the following archi- tectural features:

Two processing elements (PEx and PEy), each containing 32-bit IEEE floating-point computation units—multiplier, arithmetic logic unit (ALU), shifter, and data register file

Program sequencer with related instruction cache, interval timer, and data address generators (DAG1 and DAG2)

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Getting Started With SHARC Processors

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Analog Devices 82-003536-01 manual What are Sharc Processors? Common Architectural Features

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