The Evaluation Process

ease of use with the ability to import C header files, allowing for symbolic references into arbitrarily complex C data structures. Binary data can be included directly into assembly source files, creating an easy way to add blocks of static data (such as audio samples and bitmaps) to an applica- tion. The VisualDSP++ linker is fully multicore and multiprocessor (MP) aware, allowing for the creation of cross-linked, multi-executable applica- tions in a single pass. Other powerful capabilities of the linker include dead code and data elimination, code and data overlays, and section spill- ing (for example, automatic overflow from internal to external memory).

VisualDSP++, when used in combination with ADSP-2146x SHARC pro- cessors, is designed to take advantage of the VISA (Variable Instruction Set Architecture) feature. The code generation tools provide the option to turn on or off the use of the VISA feature. The user must place code to be compressed into the correct segment in the linker definition file. Com- pressed or uncompressed code is then generated by the VisualDSP++ tool chain without further user effort.

Leverage-Proven Application Infrastructure

VisualDSP++ goes beyond robust code generation tools, providing consid- erable application infrastructure and middleware out of the box to speed application development.

The VisualDSP++ kernel (VDK) is a robust, royalty-free, real-time operat- ing system (RTOS) kernel. This pre-emptive multitasking kernel incorporates state-of-the-art scheduling and resource allocation techniques tailored specifically for the memory and timing constraints of DSP pro- gramming. The kernel facilitates development of performance-structured applications using frameworks of template files. It provides essential ker- nel features in a minimal footprint. Features include a fully pre-emptive scheduler (time slicing and cooperative scheduling are also supported), thread creation, semaphores, interrupt management, inter-thread messag- ing, events, and memory management (memory pools and multiple heaps). In MP environments, MP messaging is also provided.

Getting Started With SHARC Processors

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Analog Devices 82-003536-01 manual Leverage-Proven Application Infrastructure

82-003536-01 specifications

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