Power-Up Timing1 | Analog Devices ADSP-TS201S instruction

ADSP-TS201S

Table 25. Power-Up Timing1

Parameter		Min	Max	Unit
Timing Requirement
tVDD_DRAM	VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable	>0		ms

1For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.

VDD

VDD_A

VDD_IO

tVDD_DRAM

VDD_DRAM

Figure 12. Power-Up Timing

Table 26. Power-Up Reset Timing

Parameter						Min	Max	Unit
Timing Requirements
tRST_IN_PWR		Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK, and Static/
tRST_IN_PWR	RST_IN
	Strap Pins Stable					2		ms
1
1	TRST Asserted During Power-Up Reset					100 × tSCLK		ns
tTRST_IN_PWR	TRST Asserted During Power-Up Reset					100 × tSCLK		ns
Switching Characteristic
tRST_OUT_PWR			Deasserted After		Deasserted	1.5		ms
tRST_OUT_PWR	RST_OUT		Deasserted After	RST_IN	Deasserted	1.5		ms

1Applies after VDD, VDD_A, VDD_IO, VDD_DRAM, and SCLK are stable and before RST_IN deasserted.

RST_IN

RST_OUT

TRST

SCLK, VDD, VDD_A, VDD_IO, VDD_DRAM

STATIC/STRAP PINS

tRST_IN_PWR

tTRST_IN_PWR

tRST_OUT_PWR

Figure 13. Power-Up Reset Timing

Rev. C Page 26 of 48 December 2006

Page 26

Image 26

Analog Devices ADSP-TS201S specifications Power-Up Timing1, Power-Up Reset Timing

Contents

ADSP-TS201S ADSP-TS201S Benchmark Speed Cycles General-Purpose Algorithm Benchmarks at 600 MHzClock FIR filter per real tap 83 ns Dual Integer ALU Ialu Dual Compute BlocksData Alignment Buffer DAB Interrupt Controller Program SequencerDSP Memory Flexible Instruction Set External Port OFF-CHIP MEMORY/PERIPHERALS Interface Internal Space Multiprocessor Interface DMA ControllerHost Interface Sdram Controller DMA controller provides these additional features No Boot, Run from Memory Addresses Timer and GENERAL-PURPOSE I/OReset and Booting Link Ports Lvds Development Tools Power DomainsFiltering Reference Voltage and Clocks Evaluation KIT Additional Information Sclk Ratio Pin Definitions-Clocks and ResetSignal Type Term Description Ratio Pin Definitions-External Port Bus Controls ACK T/OD Signal Type Pin Definitions-External Port Arbitration Sample the data instead of the TigerSHARC Pin Definitions-External Port DMA/FlybyDSP performs DMA transfers according to the DMA Makes Hdqm Pin Definitions-External Port Sdram ControllerLdqm SDA10 Pin Definitions-Flags, Interrupts, and Timer Pin Definitions-JTAG Port Signal Type Term Description CONTROLIMP1 Pin Definitions-Link PortsCONTROLIMP0 DS1 DS2-0 Drive Output Pins Strength Impedance Pin Definitions-Power, Ground, and ReferenceDriver Mode Impedance Control Selection Pin Rstin = Pin Definitions-I/O Strap PinsType at Signal Reset Operating Conditions Sclkvref Maximum Duty Electrical CharacteristicsMaximum Duty Cycle for Input Transient Voltage VIN Max VIN Min Cycle2 Absolute Maximum Ratings Package InformationESD Sensitivity Package Brand Information General AC Timing Timing SpecificationsAC Asynchronous Signal Specifications Reference Clocks-Core Clock Cclk Cycle Time Sclkrat = 5⋅, 7⋅ Parameter Description Min Max Unit Reference Clocks-System Clock Sclk Cycle TimeReference Clocks-JTAG Test Clock TCK Cycle Time Parameter Description Min Max Unit Power-Up Timing1 Power-Up Reset Timing Normal Reset Timing On-Chip Dram Refresh1 AC Signal Specifications OutputDisable Max Jtag SYS 11 Jtag System Pins +2.5 +10.0 +12.0 DS2-0 Static Pins-Must Be ConstantStrap Pins Strap SYS 9 Parameter Description Test Conditions Min Max Unit Link Port Lvds Transmit Electrical CharacteristicsLink Port Lvds Receive Electrical Characteristics VOD Link Port-Data Out Timing Parameter Description Min Max Unit Link Ports-Output Clock Link Ports-Transmission End and Stops Link Port-Data In Timing LxBCMPI Hold Figure Link Ports-Data Input Setup and Hold1 Output Drive Currents Typical Drive Currents at Strength Output Disable Time Test Conditions Output Enable Time Capacitive Loading Times Andfall Rise Fall Time Environmental Conditions Thermal CharacteristicsThermal Characteristics for 25 mm × 25 mm Package Parameter Condition Typical Unit Ball Bgaed PIN Configurations Ball No Signal Name Ball 25 mm × 25 mm Bgaed Ball Assignments L0DATI1N Sdcke SCLKRAT1L0ACKO L0DATI3N DS1 CONTROLIMP1 TDO FLAG3 DS2 Enedreg TCKID2 TDI TMR0E L1CLKINN Package Ball Attach Type Solder Mask Opening Ball Pad Size Surface Mount DesignBGA Data for Use with Surface Mount Design Ball Bgaed Nonsolder Mask Defined Nsmd Mm diameter BP-576 Operating Voltage Option Description Temperature Instruction On-Chip Package Model Range1 Rate2Ordering Guide Rev. C Page 47 of 48 December Rev. C Page 48 of 48 December

ADSP-TS201S

Table 25. Power-Up Timing1

Parameter

Min

Max

Unit

Figure 12. Power-Up Timing

Table 26. Power-Up Reset Timing

Deasserted

Figure 13. Power-Up Reset Timing