Analog Devices ADSP-TS201S specifications DMA controller provides these additional features

ADSP-TS201S

	ADSP-TS201S #7
	ADSP-TS201S #6
	ADSP-TS201S #5		CONTROL	ADDRESS
	ADSP-TS201S #4				DATA
	ADSP-TS201S #3
	ADSP-TS201S #2
	ADSP-TS201S #1
001	ID2–0	BR7–2,0
	RST_IN	BR1
	CLKS/REFS	ADDR31–0
		DATA31–0
LINK	LINK	CONTROL
DEVICES
	ADSP-TS201S #0		CONTROL	ADDRESS	DATA
000	ID2–0	BR7–1
		BR0
RESET	RST_IN	ADDR31–0			ADDR
	CLKS/REFS	DATA31–0			DATA	GLOBAL
	RST_OUT	RD			OE	MEMORY
						AND
	POR_IN
		WRL			WE	PERIPHERALS
CLOCK	SCLK	ACK			ACK	(OPTIONAL)
		MS1–0			CS
		BUSLOCK
		BMS			CS	BOOT
		CPA			ADDR
REFERENCE	SCLK_VREF					EPROM
REFERENCE	VREF	DPA			DATA	(OPTIONAL)
		BRST
	SCLKRAT2–0
		DMAR3–0				CLOCK
		BOFF				HOST
		HBR
	IRQ3–0					PROCESSOR
	FLAG3–0	HBG				INTERFACE
		MSH				(OPTIONAL)
	LINK
		IORD			ADDR
	LxDATO3–0P/N
		IOWR
	LxCLKOUTP/N				DATA
		IOEN
LINK	LxACKI
		MSSD3–0			CS
DEVICES	LxBCMPO					SDRAM MEMORY
		RAS			RAS
(2 MAX)	LxDATI3–0P/N					(OPTIONAL)
(OPTIONAL)		CAS			CAS
	LxCLKINP/N
		LDQM			DQM
	LxACKO

LxBCMPI			SDWE	WE
TMR0E			SDCKE
				CKE
BM
			SDA10	A10
CONTROLIMP1–0				ADDR
		CONTROL
				DATA	CLK
DS2–0	JTAG

Figure 4. ADSP-TS201S Shared Memory Multiprocessing System

external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels.

•AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer.

The DMA controller provides these additional features:

•Flyby transfers. Flyby operations only occur through the external port (DMA Channel 0) and do not involve the DSP’s core. The DMA controller acts as a conduit to trans- fer data from an I/O device to external SDRAM memory.

During a transaction, the DSP relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0); outputs the IORD, IOWR, IOEN, and RD/WR strobes; and responds to ACK.

•DMA chaining. DMA chaining operations enable applica- tions to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes.

•Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.

Rev. C Page 8 of 48 December 2006