Cypress CY7C2563KV18 Power Up Sequence in QDR-II+ Sram, PLL Constraints, VDD / Vddq, Doff DDQ

PRELIMINARY	CY7C2561KV18, CY7C2576KV18
	CY7C2563KV18, CY7C2565KV18

Power Up Sequence in QDR-II+ SRAM

QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

❐Drive DOFF HIGH.

PLL Constraints

■PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The PLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 μs of stable clock to relock to the desired clock frequency.

■Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs to lock the PLL

Figure 5. Power Up Waveforms

~ ~

K

K

	~ ~
Unstable Clock	> 20Πs Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ VDDQ	VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )
	Fix HIGH (or tie to V )
DOFF	DDQ

Document Number: 001-15887 Rev. *E Page 20 of 29

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