LSI 53C875A technical manual PCI Bus Interface Signals, System Signals, Type Strength Description

3.3 PCI Bus Interface Signals

The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, and Interrupt Signal.

3.3.1 System Signals

Table 3.2 describes the System signals.

Table 3.2		System Signals
Name	PQFP		BGA	Type	Strength	Description
CLK	145		A6	I	N/A	Clock provides timing for all transactions on the PCI bus
						and is an input to every PCI device. All other PCI signals
						are sampled on the rising edge of CLK, and other timing
						parameters are defined with respect to this edge. Clock
						can optionally serve as the SCSI core clock, but this may
						effect fast SCSI-2 (or faster) transfer rates.
RST/	144		B6	I	N/A	Reset forces the PCI sequencer of each device to a
						known state. All T/S and S/T/S signals are forced to a high
						impedance state, and all internal logic is reset. The RST/
						input is synchronized internally to the rising edge of CLK.
						The CLK input must be active while RST/ is active to
						properly reset the device.

3-4 Signal Descriptions