Sdram interface, Dras Dcas, Dclk | Texas Instruments TNETX3270

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

Terminal Functions (Continued)

SDRAM interface

TERMINAL

I/O

INTERNAL

DESCRIPTION

NAME

NO.

RESISTOR

DA13

212

DA12

210

DA11

209

DA10

207

DA09

206

DA08

205

SDRAM address bus (time-multiplexed bank, row, and column address). The address bus

DA07

204

O

None

DA13±DA00 also provides the SDRAM mode register initialization value. DA13 is the most significant

DA06

203

bit and DA00 is the least significant bit.

DA05

202

DA04

200

DA03

199

DA02

198

DA01

196

DA00

195

SDRAM column address strobe.

in conjunction with

and

determines the SDRAM

189

O

None

DCAS,

DRAS

DW,

DCAS

commands.

DCLK

193

O

None

SDRAM clock (83.33-MHz clock to the SDRAMs). SDRAM commands, addresses, and data are

sampled by the SDRAM on the rising edge of this clock.

DD31

187

DD30

186

DD29

185

DD28

183

DD27

182

DD26

181

DD25

180

DD24

179

DD23

177

DD22

176

DD21

174

DD20

173

DD19

172

DD18

171

DD17

170

SDRAM data bus (bidirectional bus used to carry SDRAM data). DD31±DD00 also output status

DD16

168

I/O

Pullup

information to indicate buffer operation type and port number. Internal pullup resistors are provided.

DD15

167

DD31 is the most significant bit and the DD00 is the least significant bit.

DD14

166

DD13

164

DD12

162

DD11

161

DD10

159

DD09

158

DD08

157

DD07

156

DD06

155

DD05

153

DD04

152

DD03

150

DD02

149

DD01

147

DD00

146

190

O

None

SDRAM row address strobe.

with

and

supplies the SDRAM commands.

DRAS

DRAS,

DCAS

DW,

191

O

None

SDRAM write select.

with

and

supplies the SDRAM commands.

DW

DW,

DRAS

DCAS,

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

Image 9

Texas Instruments TNETX3270 specifications Sdram interface, Dras Dcas, Dclk

Contents

With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch Description With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports Contents ThunderSWITCH 24/3 ETHERNET PGV Package TOP View  24/3 ThunderSWITCH Terminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³ 10-/100-Mbit/s MAC interface ports 24±26 ² Terminal Functions Dras Dcas Sdram interfaceDclk Dras Host DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QID VLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QID TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8 State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRC Mbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short frames Data transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacing Uplink pretagging Receive versus transmit priority Source Port Source-Port Pretag Encoding Received Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load Outcomes Jtag Instruction Opcodes Jtag interfaceHighz instruction LED interface LED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED display TNETX3270 TNETE2008 Terminal Mbit/s Interface Connections M03TXD M04TXD Port CLK Sync TXD3M06TXD M03COL Connecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal Function SDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization Refresh Frame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroring Flow control Port trunking/load sharing Ieee Std 802.3 flow control Collision-based flow control Pause frame reception Internal wrap test PHY TNETX3270 Duplex wrap test Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit 10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see Figure Sdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras Dcas DIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom ² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid TsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fall Mechanical Data Important Notice