Intel®
1.2Block Diagram
Figure 1. Block Diagram
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| Flash Memory | NAND | |
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| Channel 0 | Flash | |
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| Memory | ||
| Intel |
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SATA Interface | System | Flash Memory |
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Channel ... | NAND | |||
On A Chip | ||||
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| Flash | ||
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| Memory | ||
| (SOC) |
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| Flash Memory | NAND | |
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| Channel n | Flash | |
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| Memory |
1.3Architecture
The Intel
2.0Certifications
Table 1. | Device Certifications | |
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Certification | Description | |
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CE Compliant |
| Indicates conformity with the essential health and safety requirements set out in European |
| Directives Low Voltage Directive and EMC Directive. | |
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UL Certified |
| Underwriters Laboratories, Inc. Component Recognition |
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| Compliance with the Australia/New Zealand Standard AS/NZS3548 and Electromagnetic |
| Compatibility (EMC) Framework requirements of the Australian Communication Authority | |
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| (ACA). |
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BSMI Compliant |
| Compliance to the Taiwan EMC standard “Limits and methods of measurement of radio |
| disturbance characteristics of information technology equipment, CNS 13438 Class B.” | |
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Intel® | ||
Advance Product Manual | July 2008 | |
6 |
| Order Number: |