Intel AI5VG user manual CPU to PCI Write Buffer, PCI Dynamic Bursting, PCI Master 0 WS Write

Page 50

Chapter 7 LANDesk User Guide

CPU to PCI Write Buffer

When enabled, this option increase the efficiency of the PCI bus to and speed up the execution in the processor. By default, this field is set to Enabled.

PCI Dynamic Bursting

When enabled, this option combines several PCI cycles into one. By default, this field is set to Disabled.

PCI Master 0 WS Write

When enabled, this option increases the write cycle speed. By default, this field is set to Disabled.

PCI Delay Transaction

When enabled, this option delays PCI data transaction. By default, this field is set to Disabled.

PCI Master Read Prefetch

When this item is enabled, the system is allowed to prefetch the next read and initiate the next process. By default, this field is set to Disabled.

PCI#2 Access #1 Retry

This item enables PC#2 Access #1 attempts. By default, this field is set to Disabled.

PCI Master 1 WS Write

When enabled, writes to the PCI bus are executed with 1 wait states. By default, this field is set to Disabled.

PCI Master 1 WS Read

When enabled, reads to the PCI bus are executed with 1 wait states. By default, this field is set to Disabled.

PCI IRQ Activated by

This field allows you to select the method by which the PCI bus recognizes that an IRQ service is being requested by a device. The default value is Level.

46

AI5VG Pentium VP3 Baby AT Motherboard User’s Manual

Image 50
Contents AI5VG Page Contents Bios Configuration Checklist IntroductionMain Memory Main ProcessorL2 Cache Memory TypeWindows 95 Shut-Down CPU Temperature SensorOnboard Bus Mastering Eide AGP Support Accelerated Graphics PortHardware Description Layout of the AI5VG Motherboard Processor and CPU Voltage L2 Cache MemoryBank0 Bank1 Total Memory 8MBDMI Desktop Management Interface BiosBank0 DIMM2 Bank1 DIMM1 Total Memory ISA Plug and Play PnP ExtensionOnboard PCI Eide Onboard CPU Temperature SensorPower Management Onboard Multi-I/OAddress Device Description I/O Port Address MapDMA Channels Level Function Interrupt Request Lines IRQAccelerated Graphics Port AGP Slot Hardware Settings Jumper Locations of the AI5VG SW11-8 CPU Frequency Selector For Intel Pentium CPU Bus Clock MutiplierFor Cyrix 6x86, 6x86L CPU SW21-4 CPU Voltage Selector For Dual Voltage CPU Intel P55C, Cyrix 6x86L/MX, AMD K6K6-233 35∝ JP5 Clear Cmos Selection Installation Connector Location on the AI5VG I/O Connectors J3 Pin # Description Wire ColorSignal Name Pin # J2 ATX Power Supply ConnectorJ1, J4 AT Keyboard and PS/2 Mouse Connectors J1 AT Keyboard Connector Pin # Signal NameJ7, J6 Serial Ports J8 Floppy Drive ConnectorPin # Signal Name RM/LCJ11 Secondary IDE Connector Signal Name Pin # J9, J11 Eide ConnectorsJ9 Primary IDE Connector Signal Name Pin # 10 J5 USB Connector J10 Parallel Port ConnectorJ15 IrDA Connector USB USB+13 J20 Front Bezel Connector 11 J13 Wake on LAN Connector12 J14 CPU Fan Power Connector Power LED and Keylock Pins 11 Speaker Pins 1J20 Pin # Signal Name ATX Power on Switch Pins 7Reset Switch Pins 9 Bios Configuration AGP LANDesk User Guide Bios Introduction Bios SetupStandard Cmos Setup Standard Cmos Setup DatePrimary HDDs / Secondary HDDs Mode for IDE HDD only AutoTime LBAVideo Floppy 3 Mode SupportDrive a / Drive B Halt OnCPU Internal Cache / External Cache Bios Features SetupVirus Warning Boot Up Floppy Seek Quick Power On Self TestBoot Sequence Boot Up NumLock StatusVideo Bios Shadow Typematic Rate SettingTypematic Delay Msec Typematic Rate Chars/SecChipset Features Setup Cache Timing Video Bios CacheableSystem Bios Cacheable Memory Hole at 15MB AddrPower Management Setup IRQ4 COM1Suspend Mode HDD Power DownDoze Mode PM Control by APMPM Events Reset Configuration Data PNP/PCI ConfigurationPNP OS Installed Resources Controlled byCPU to PCI Write Buffer PCI Delay TransactionPCI#2 Access #1 Retry PCI Dynamic BurstingPCI IDE IRQ Map To Load Bios Defaults Load Setup DefaultsIntegrated Peripherals IDE Prefetch ModeIDE HDD Block Mode OnChip Primary/Secondary PCI IDEIDE Primary/Secondary Master/Slave Udma Uart 2 ModeOnboard Parallel Mode Onboard FDD ControllerSupervisor / User Password Supervisor PasswordIDE HDD Auto Detection HDD Low Level FormatSave & Exit Setup Exit Without Saving