Intel 83C51FA, 80C51FA specifications Symbol Parameter Min Typ Max Unit Test Conditions, Rrst, Cio

AUTOMOTIVE 80C51FA/83C51FA DC CHARACTERISTICS: (TA e b40§C to a125§C; VCC e 5V g10%; VSS e 0V) (Continued)

	Symbol	Parameter		Min		Typ		Max	Unit	Test Conditions
	ITL	Logical 1 to 0 Transition Current				b265		b650	mA	VIN e 2V
		(Ports 1, 2, and 3)
	RRST	RST Pulldown Resistor		40	100			225	KX
	CIO	Pin Capacitance			10				pF	@1MHz, 25§C
	ICC	Power Supply Current:						40	mA	(Note 3)
		Running at 12 MHz (Figure 5)
		Idle Mode at 12 MHz (Figure 5)						15	mA
		Power Down Mode (IPD)						150	mA
NOTES:
1.	Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3.
	The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
	transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
	signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
	with a Schmitt Trigger Strobe input.
2.	Capacitive loading on Ports 0 and 2 cause the VOH on ALE and					PSEN	to drop below the 0.9 VCC specification when the
	address lines are stabilizing.
3.	See Figures 6±9 for test conditions. Minimum VCC for Power Down is 2.0V.
4.	Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and
	5.0V.
5.	Under steady state (non-transient) conditions, IOL must be externally limited as follows:
	Maximum IOL per Port Pin:		10 mA
	Maximum IOL per 8-Bit Port -		26 mA
		Port 0:
		Ports 1, 2, and 3:	15 mA
	Maximum Total IOL for all Output Pins:		71 mA
	If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
	than the listed test conditions.
6.	Contact Intel for design-in information.

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