Description of Operating Precautions, Details

Operating Precautions for VR4133 TM

(B) Description of Operating Precautions

No. 1 Simultaneous locking of cache lines with the same index (Specification change notice)

Details

Simultaneous locking of two cache lines with the same index (i.e. in both cache ways) is prohibited.

No. 2 Reception of non IEEE802.3 conformant packages (Specification change notice)

Details

In case of the reception of a non-IEEE802.3 conformant 18-Byte length Ethernet packet, the internal flow control logic, statistic counter and receive status indicator may no longer work properly. To avoid this situation, control Ethernet reception as follows:

(1)Check the FTTYP(27:25) bits of the receive descriptor. If the FTTYP descriptor indicates a control frame or a pause control frame, check the frame type additionally by inspecting the Length/Type field of the Ethernet frame. If this is inconsistent with the content of the FTTYP bits, ignore the FTTYP bits.

(2)Additionally the following statistics counters must be adjusted based on the content of the Length/Type field:

RXCFC0/1 (0x0f00 1554/1854) RXPFC0/1 (0x0f00 1558/1858) RXUOC0/1 (0x0f00 155c/185c)

(3)Flow control must be stopped by setting the RXCF bit in the MACC10/1 registers (0x0f00 1400/1700) to 0y0.

No. 3	Register content in Ether0/1 blocks
	(Direction of usage)
	Details
	When burst cycles occur on the internal bus, the content of registers in the Ether0/1 blocks can
	be changed accidentally, because data information is mistaken as address. To avoid this, the
	following countermeasures must be taken:

(1)The data cache must not be used.

(2)The processor must be run in 32-bit mode.

(3)The processor must be operated in user- or supervisor mode.

(4)The DTBS(1:0) bits in the XMT_CFGR0/1 registers (0x0f00 1600/1900) must be set to 0y00.

No. 4	Read access from external PCI master
	(Specification change notice)
	Details
	In case that an external PCI master tries to read data from VR4133 memory via PCI DMA,
	VR4133 may respond with wrong read data. To avoid this situation, one of the following
	countermeasures must be taken:
	(1)	Do not use PCI DMA (memory -> PCI).
	(2)	If PCI DMA is used, don’t use an external PCI master, that issues read requests to VR4133.

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