IBM 25CPC710 user manual Processor Interface Voltage Level and Bus Speed Differences

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Processor Interface:

vVoltage Level and Bus Speed Differences

ØThe CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX, and 750CXe processors. This is a change from the previous revision.

vI/O Signal New Functionality

ØSet bit 18 of 60x Bus Arbiter register (system register CPC0_ABCNTL) to 1 to allow the signal level of SYS_TA_ to be confirmed and held at a high logic level (after precharging) as soon as the CPC710 DD3.x exits the RESET state. This is to allow for proper operation in systems with high loads on the CPU bus.

vI/O Signal Additional Functionality for 4-way Processor Support

ØComing out of reset, the 60x bus arbitration logic of the CPC710 DD3.x defaults to the same dual processor mode used in the CPC710 DD2. To enable 4-way arbitration, the Master CPU should set chip control register CPC0_ABCNTL [17] to a “1”. Then the SYS_HRESET2_, SYS_HRESET3_, SYS_SRESET2_ and SYS_SRESET3_ signals will go inactive, allowing CPUs 2 and 3 to exit the reset state.

ØThe two Reset registers CPC0_RSTR and CPC0_SRST have been modified to include bits to support program control operation of hard and soft reset signals for the additional processors.

§Connectivity Reset Register bits CPC0_RSTR [4:5] controls signals SYS_HRESET2_ and SYS_HRESET3_ respectively. CPU Soft Reset Register bits CPC0_SRST [4:5] controls signals SYS_SRESET2_ and SYS_SRESET3_ respectively

§The CPC0_PIDR Register has been modified to allow identification of each of the 4 processors; if CPC0_PIDR [24:31] is read as 'h00’ it indicates the Processor corresponding to BR0_/BG0_ is active. Valid values for these bits are:

∙= 0x00==> Processor corresponding to BR0_/BG0_

∙= 0x01 ==> Processor corresponding to BR1_/BG1_

∙= 0x02 ==> Processor corresponding to BR2_/BG2_

∙= 0x03 ==> Processor corresponding to BR3_/BG3_

vI/O Signals for 4-way Processor Support

ØThe signals SYS_MCP0: 3 are used to indicate to the CPUs that the CPC710 has detected an error condition and a machine check is required. To help reduce pin count, output signals SYS_MCP2_ and SYS_MCP0_ are generated from one internal signal source. SYS_MCP3_ and SYS_MCP1_ also share a common internal signal source.

ØThe System Error Status Register has not been modified and only errors that occur with Processor 0 or 1 can be detected and reported.

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Version 1.0

11/08/01

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Contents Abstract OverviewProcessor Interface Voltage Level and Bus Speed Differences O Signal New FunctionalityO Signals for 4-way Processor Support Supported Memory Types Memory Interface Extended Sdram AddressingExtended Memory Size Maximum Number of Memory Banks Decreased from 8 toPCI-32 Interface Now Supports External Arbiter Usage Power and PLL New Supply VoltagesExtended Addressing of PCI Memory Packaging Changes FC-PBGA Package instead of Cbga Following I/Os are new on the DD3 revision O Pins MultiplexedO Pin Additions Following I/Os are multiplexed on the DD3 revisionPerformance Enhancements and Improvements IBM CorporationIBM
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