Sun Microsystems manual Sun Sparc Enterprise T5120 and T5220 Servers

6 The Evolution of Chip Multithreading (CMT) Sun Microsystems, Inc.

Chip multithreading provides real value since it increases the ability of the execution pipeline to do actual work on any given clock cycle. Utilization of the processor pipeline is greatly enhanced since a number of execution threads now share its resources. The negative effects of memory latency are effectively masked, since the processor and memory subsystems remain active in parallel to the processor execution pipeline. Because these individual processor cores implement much simpler pipelines that focus on scaling with threads rather than frequency (emphasizing TLP over ILP), they are also substantially cooler and require significantly less electrical energy to operate. This innovative approach results in CoolThreads processor technology — multiple physical instruction execution pipelines (one for each core), with multiple active thread contexts per core.

The UltraSPARC® T2 Processor with CoolThreads Technology

Unlike complex single-threaded processors, CMT processors utilize the available transistor budget to implement multiple hardware multithreaded processor cores on a chip die. The UltraSPARC T2 processor takes the CMT model to the next level, providing up to eight cores with each core supporting up to eight threads via two independent pipelines per core — effectively doubling the throughput of the UltraSPARC T1 processor. In addition, the UltraSPARC T2 processor uses this transistor budget to implement the industry’s first massively threaded System on a Chip (SoC), with a single processor die hosting:

•Up to 64 threads per processor (up to eight cores supporting eight threads each)

•On-chip Level-1 and Level-2 caches

•Per-core floating point capabilities

•Per-core cryptographic acceleration

•Two on-chip 10 Gb Ethernet interfaces

•On-chip PCI Express interface

Through this SoC design, the UltraSPARC T2 processor significantly enhances the general purpose nature of the CPU by building in eight floating point units (1 per core). Enhanced floating point capabilities open the UltraSPARC T2 to the world of compute- intensive applications as well as the traditionally CMT friendly datacenter throughput applications. No-cost security and cryptographic acceleration is provided by the on-chip, per-core streaming accelerators. In addition, the ability to move data in and out of the processor is significantly aided by an integrated PCI-Express interface and dual

10 Gigabit Ethernet interfaces.

Sun SPARC® Enterprise T5120 and T5220 Servers

Sun SPARC Enterprise T5120 and T5220 servers (Figure 2) are designed to leverage the considerable resources of the UltraSPARC T2 processor in the form of cost-effective general-purpose platforms. These systems deliver up to twice the throughput of their