OPT-622A1F1R
Pin Definition
PIN
Symbol
Functional description
1 | GND |
2RD (+)
3RD
4 | SD |
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5 | VccR |
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6 | VccT |
7TD
8TD (+)
9GND
Receiver Signal Ground
Receiver Data Out
Transmitter Power Supply
Transmitter Data In Inverted (LVPECL or PECL) Transmitter Data In
Pin Descriptions
Pin 1 Receiver Signal Ground, GND
Directly connect these pins to the ground plane.
Pin 2 Receiver Data Out
PECL logic family. Output external biased and internal DC coupled.
Pin 3 Receiver Data Out Inverted (LVPECL), RD
PECL logic family. Output external biased and internal DC coupled.
Pin 4 Receiver Signal Detect (LVPECL), SD
PECL logic family. Normal Operation: Logic “1” Output; Fault Condition: Logic”0” Output.
Pin 5 Receiver Power Supply, VccR
Provide +3.3V dc power supply.
Pin 6 Transmitter Power Supply, VccT
Provide +3.3V dc power supply.
Pin 7 Transmitter Data In Inverted (LVPECL), TD
Pin 7 Transmitter Data Input Inverted (LVPECL), TD
Pin 8 Transmitter Data In
Pin 8 Transmitter Data Input
Pin 9 Transmitter Signal Ground, GND
Directly connect these pins to the ground plane.
| 3 | www.deltaww.com |
DELTA ELECTRONICS, INC. | Jan., 2008 | |
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| Rev.：0D |