Contents
Chapter | 1 | Overview | 2 |
| 1.1 | Introduction | 2 |
| 1.2 | Hardware Specifications | 5 |
| 1.3 | Safety Precautions | 7 |
| 1.4 | Chassis Dimensions | 8 |
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| Figure 1.1:Chassis Dimensions for CeleronM 1GHz .... | 8 |
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| Figure 1.2:Chassis for Pentium 1.8GHz or Faster CPU | 9 |
| 1.5 | Packing List | 10 |
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| Figure 1.3: Accessories | 10 |
Chapter | 2 | Hardware Functionality | 12 | |
| 2.1 | Introduction | 12 | |
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| Figure 2.1:Front Panel of | 12 |
| 2.2 | 13 | ||
| 2.3 | 13 | ||
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| 2.3.1 16C550 UARTs with | 13 | |
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| 2.3.2 | 13 | |
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| 2.3.3 Automatic Data Flow Control Function for | 13 | |
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| 2.3.4 | 14 | |
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| Figure | 14 |
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| Figure | 14 |
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| 2.3.5 | 14 | |
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| Table 2.1:Auto Flow & | 15 |
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| 2.3.6 IRQ, I/O Address and Transmission Rate Setting | 15 | |
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| Table 2.2:IRQ Setting via Switch 1 at SW3 | 16 |
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| 2.3.7 | Table 2.3:Transmission Rate (Switch 2 at SW3) | 16 |
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| Termination Resistor (JP6) | 17 | |
| 2.4 | LAN: Ethernet Connector | 17 | |
| 2.5 Onboard Isolated Digital Input | 17 | ||
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| 2.5.1 | Pin Assignments | 17 |
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| Figure 2.4:Digital Input Connector Pin Assignments .. | 17 |
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| 2.5.2 | Table 2.4:Digital Input Connector Signal Description | 18 |
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| Isolated Inputs | 18 | |
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| Figure 2.5:Isolated Digital Input Connection | 18 |
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| 2.5.3 Interrupt Function of the DI Signals | 19 | |
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| 2.5.4 | IRQ Level | 19 |
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| 2.5.5 | Interrupt Control Register | 19 |
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| Table 2.5:Interrupt Control Register Bit Map | 19 |
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| 2.5.6 Interrupt Enable Control Function | 20 | |
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| Table 2.6:Interrupt Disable/Enable Control | 20 |
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| 2.5.7 Interrupt Triggering Edge Control | 20 | |
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| 2.5.8 | Table 2.7:Interrupt Triggering Edge Control | 20 |
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| Interrupt Flag Bit | 20 | |
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| Table 2.8:Interrupt Flag Bit Values | 20 |
| 2.6 Onboard Isolated Digital Output | 21 |
vii | Table of Contents |