Texas Instruments 4Q 2006 manual PCI Express, Key Benefits, Target Markets

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PCI Express®

PCI Express® Bridge Chip

XIO2000A

Get samples, datasheets, EVMs and app reports at: www.ti.com/sc/device/XIO2000A

TI’s PCI Express bridge chip, the XIO2000A, is an industry first. It is designed for seamless migration from the legacy PCI to the PCI Express interface. It bridges an x1 PCI Express bus to a 32-bit, 33/66-MHz PCI bus capable of supporting up to six PCI devices downstream. The XIO2000A fully supports PCI Express rates of 2.5 Gbps. Its architecture supports the PCI

2.3interface. The chip’s design enables PC and I/O add-on card manufacturers to begin transitioning to native PCI Express technology while preserving compatibility with existing PCI system software and firmware.

Key Features

Compliant with PCI Express to PCI/PCI-X Bridge Specification Revision 1.0

Compliant with PCI Express Base Specification 1.0a

Compliant with PCI Local Bus Specification rev 2.3

Utilizes 100 MHz differential PCI Express Common Reference Clock or 125 MHz Single-Ended Reference Clock

Full PCI Local Bus 66 MHz/32-bit Throughput

Wake/Beacon Event Support

Robust Architecture to Minimize Latency

Key Benefits

Built-in adaptive receiver equalizer

• Improves jitter tolerance thereby

reliably increasing PCB trace, or cable

length, supported by the XIO2000

• Seven buffered PCI clock outputs

(33 MHz or 66 MHz)

• Reduces external components, costs

and premium board space

32-bit secondary PCI bus with 33-MHz or

66-MHz clocking option

• Customizes to meet the needs of high-

performance or low-power applications

• Proven compatibility with various PCI

Express chipsets and PCI add-in cards

• Rigorous field testing with major root

 

PCI Express

PCI Express

 

Transmitter

 

Receiver

Power

 

 

GPIO

Mgmt

 

 

 

 

 

Clock

Configuration and

Serial

Generator

 

Memory Register

EEPROM

Reset

 

 

Serial IRQ

Controller

 

 

 

 

 

 

 

PCI Bus Interface

 

complex device and numerous PCI

add-in cards

• Compact footprint

• Allows placement in ExpressCard and

mini-PCI cards in limited board space

• Advanced power management

features

• Software programmable and hardware

autonomous power management

features for low-power applications

such as ExpressCard

XIO2000A functional block diagram.

 

 

Vaux

PCI

Upstream

Auxilliary

Express

PCI Express

Power

Reference

Device

 

Clock

 

 

System Side

 

 

 

PCI Express

 

 

Link

 

 

 

Serial

 

 

EEPROM

GPIO

XIO2000A

Miscellaneous

 

 

Serial

 

PCI Bus functions:

 

CLR_RUN, PWR_OVRD,

Interrupt

 

 

LOCK, M6 6EN,

Controller

 

 

PME, External Arbiter

 

 

Target Markets

The XIO2000A meets the needs of multiple market segments, including desktop and mobile PC, server, storage, PC add-in cards and embedded systems.

PCI Bus—32 bit, 33/66 MHz

Typical system implementation.

Interface Selection Guide

Texas Instruments 4Q 2006

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Contents Interface Selection Guide Table of Contents Interface Selection GuideInterface Selection Guide Clock Distribution Circuits pTechnical Information LVDS, xECL, CMLDesign Considerations Lvds Family of ProductsPecl Selection Guide Texas Instruments 4QLvds Selection Guide Dual Family SupplyDevice Pin/Packages Price Single Family Quad FamilyMultipoint Lvds Lvds FeaturesMultipoint-LVDS M-LVDS Lvds Devices from TIHalf Part-toDigital Isolators Mbps Jitter To ensure signal integrityKey Features Digital Isolators Selection GuideRS-485/422 RS-485/422 Family of ProductsNodes FeaturesNo. Dr/Rx SoicRS232 IEC6100-4-2 Level ESD-Protected Devices Flexible power-saving options enable longer battery lifeRS-232 Space-saving QFN package options for portable applicationsDevice Drivers ReceiversPin/Packages Price RS-232 Selection Guide Pin/Package PriceUart Family of Products Programmable sleep mode and low-power modeUARTs Universal Asynchronous Receiver/Transmitters 64-byte FIFOs available 3-, 2.5- and 1.8-V supplyAsynchronous Communications Element with Autoflow Control UARTs Universal Asynchronous Receiver/TransmittersUart Selection Guide PDAs MP3 players Gaming systems Modems Serial ports TelecomSelection Guide Can 3.3-V and 5-V High-Speed can TransceiversCan Transceiver Selection Guide Standard Compliant ProtocolsFlatLink 3G Selection Guide Flatlink 3GFlatLinkTM 3G Display SerDes for Mobile Phones 1755Buffer SerDes Solutions-Frontplane/BackplaneSerDes Serial Gigabit Transceivers and Lvds PhotoGigabit Xaui Ethernet SerDes Serial Gigabit Transceivers Selection GuideGigabit Ethernet/FibreChannel Lvds Serdes22 DVI/PanelBus High Bandwidth Digital Content Protection HdcpContent protection for video sent over DVI Hdcp ElementsDesktop LCD monitors DLP and LCD projectors Digital TVs Digital visual interface DVI compliantSet-top boxes Max ps Intra-Pair ps Inter-Pair Clock P-P Data P-PJitter 40QFNTransfer Type Universal Serial Bus USBSpeed USB-to-Serial BridgeUSB Hub Controllers and Peripheral Devices USB Family of ProductsPackage USB Power Managers Family of Products Port USB Hub Power ControllersUniversal Serial Bus USB Power Managers USB Power Managers Selection GuidePCI Express DeviceClassifications PCI Express Key BenefitsTarget Markets Target Market ExpressCards PC Add-In Cards PC MotherboardsPainful and not robust TX BlockRX Block Capabilities PCI BridgesTwo 32-bit, 33- or 66-MHz buses FunctionalityCardBus Power Switches Power Distribution Devices Family of ProductsEnable Predecessor Transition TimeIN1 to IN2 Link-Layer Selection Issues 36 1394 FireWirePhysical-Layer Selection Issues OverviewFaster speeds from 800 Mbps to 3200 Mbps 1394b AdvantagesReal-time streaming of audio and video More efficient Boss arbitrationFireWire Key Features ApplicationsSignal Integrity TI vs Competition Conn. Conn. Conn. Conn. Conn. ConnDevice Description Price Gtlp Gunning Transceiver Logic PlusGtlp Selection Guide Other LiteratureVME HighlightsClock Distribution Circuits SN65HVD3085E SN65HVD3082ECross-Reference Guide SN65HVD3088ECross-Reference Guide SN65LVDT3486BPericom SN65LVDT9637BDevice Index Texas InstrumentsInternet Product Information CentersImportant Notice