Family 10h AMD Phenom II Processor Features

PID:46878 Rev:3.04 - February 2009

Family 10h AMD Phenom™ II Processor Product Data Sheet

1 Family 10h AMD Phenom™ II Processor Features

The following is a list of features and capabilities of the Family 10h AMD Phenom™ II processor.

•Including support for SSE, SSE2, SSE3, SSE4a, ABM, MMX™, 3DNow!™ technology and legacy x86 instructions

•Runs existing operating systems and drivers

•Local APIC on the chip

•AMD64 technology instruction set extensions

•64-bit integer registers, 48-bit addresses

•Sixteen 64-bit integer registers

•Sixteen 128-bit SSE/SSE2/SSE3/SSE4a registers

•AMD Balanced Smart Cache

•Discrete L1 and L2 cache structures for each core

•Shared L3 cache structure

•Machine Check Architecture

•Includes hardware scrubbing of major ECC protected arrays

•Cache Structures

•64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache

•Two 64-bit operations per cycle, 3-cycle latency

•64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache

•With advanced branch prediction

•512-Kbyte 16-Way Associative ECC-Protected L2 Cache

•Exclusive cache architecture storage in addition to L1 caches

•6128-Kbyte (6-Mbyte) Maximum, 64-way Maximum Associative ECC-Protected L3 Cache

•Shared cache architecture storage in addition to exclusive L1 and L2 caches

•2-cycle latency improvement for Phenom II processors

•Floating-Point Unit

•AMD Wide Floating-Point Accelerator

•128-bit Floating-Point Unit (FPU)

•SVM disable and lock

•Nested paging

•Rapid Virtualization Indexing

•Improved world-switch speed for Phenom II processors

•Multiple low-power states

•AMD Cool‘n’Quiet™ 3.0

•45-nm process for decreased power consumption

•Enhanced AMD PowerNow!™ Technology

•AMD Smart Fetch Technology

•AMD CoolCore™ Technology

•Enhanced L3 clock-gating for Phenom II processors

•Dual Dynamic Power Management