Application Note
46959A - March 2009
3.4Other Information and Restrictions
The LX processor/DDR2 solution does not do DQS train- ing. The LX processor’s memory controller does not have the adjustability to make this worthwhile, and the speeds are slow enough that this is not a problem.
The memory must be organized with 4 component banks. This means that only 512Mbits, and lower, devices are sup- ported. In addition, the memory controller only supports 1 or 2 ranks. Any other configurations should be avoided.
The DRAM must support a CAS# Latency of 2 clocks. A DIMM’s SPD may not indicate that this is supported, due to the higher typical operating frequencies of the memory. The BIOS may determine that CL=2 is possible by consid- ering the fundamental access time of the memory (i.e., cycle time multiplied by the normal CAS# Latency). The reason for this restriction is that the LX processor’s mem- ory controller must operate with a Write Latency of 1 clock. DDR2 defines CAS# Latency equal to Write Latency + 1.
Supporting CL=2 at higher frequencies implies that the memory must be of higher performance. To run the mem- ory at 166MHz, this means that the memory should have an access time of 12ns. 133MHz requires 15ns.
The typical LX processor/DDR2 implementation will run the memory at lower frequencies than average. While 166MHz is within the DDR2 specification, some memory vendors may recommend operating with the DLL disabled. The cus- tomer should investigate this with their memory supplier.
Some DRAM modules may operate at higher frequencies by raising their supply voltage. The customer should con- sult the memory manufacturer before taking this approach. The BIOS may implement an algorithm that accounts for the higher frequency. AMD has seen only limited success with this technique.
AMD Geode™ LX Processor DDR2 BIOS Porting Guide | 7 |