SUPER MICRO Computer X7SLA-L, X7SLA-H Chipset Overview, Graphics Memory Controller Hub Gmch

Chapter 1: Introduction

1-2 Chipset Overview

The Intel® 82945GC contains two components: GMCH (North Bridge) and ICH7R (South Bridge). The GMCH is used for the host bridge, and the ICH7R, for the I/O subsystems.

Graphics Memory Controller Hub (GMCH)

The GMCH manages the data flow between its four interfaces: the processor interface (FSB), the system memory interface (DRAM controller), the integrated graphics interface, the External Graphics interface, and the I/O Controller through DMI interface. It provides bus arbitration between the four interfaces when each initiates transactions. The GMCH supports a 32-byte Cache Line, decoding up to 4 GB (2GB for the 945GC) of the CPU's usable memory address space. The GMCH also supports one or two channels of SDRAM and the PCI Express-based graphics attached devices.

The Intel® 945GC platform supports the seventh generation I/O Controller Hub (In- tel® ICH7R) to provide a multitude of I/O related features. The Direct Media Interface (DMI) provides the chip-to-chip connection between the GMCH and the ICH7R.

Intel® I/O Controller Hub 7R (ICH7R)

The I/O Controller (ICH7R) provides the data buffering and interface arbitration required for the system to operate efficiently. It also provides the bandwidth needed for the system to maintain its peak performance. The ICH7R supports PCI slots, Se- rial ATA ports, USB 2.0 ports and dual channel IDE devices. In addition, the ICH7R offers the Intel Matrix Storage Technology which provides various RAID options for data protection and rapid data access. It also supports the next generation of client management through the use of PROActive technology in conjunction with Intel's next generation Gigabit Ethernet controllers.

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