Advanced Chipsets Features
This section describes advanced chipset features.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
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| DRAM Timing | Selectable | [By SPD] |
| Item Help |
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| CAS Latency | Time |
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| ______________________ |
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| Active to | Precharge | Delay | [8] |
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| Menu Level X |
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| DRAM RAS# | to CAS# Delay | [4] |
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| DRAM RAS# | Precharge |
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| System BIOS | Cacheable | [Enabled] |
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| Video BIOS Cacheable |
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| Delay Prior | to Thermal | [16 | Min] |
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| DRAM Data | Integrity | Mode | [ECC] |
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| ↑↓←→ | : Move | Enter: Select | ESC: Exit F1: General Help |
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| F5: Previous Values | F6: | F7: Optimized Defaults |
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DRAM Timing Selectable
This option permits you to either manually select memory tim- ings, or allow the SPD (Serial Presence Detect) to determine the said timings automatically. The choices are:
Manual / By SPD
Note: On all memory timing settings, a lower number is more aggressive.
CAS Latency Time
This setting controls the time delay (in clock cycles - CLKs) that passes before the DRAM starts to carry out a read com- mand after receiving it. This also determines the number of CLKs for the completion of the first part of a burst transfer. In other words, the lower the latency, the faster the transaction. The possible values are:
2 / 2.5 / 3
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