Freescale Semiconductor Block Guide Estat Eeprom Status Register, Eeprom Protection Address Range

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Block Guide — S12EETX4KV0 V00.04

Table 3-3 EEPROM Protection Address Range

EPS[2:0]

Address Offset

Protected Size

Range

 

 

 

 

 

000

$_FC0-$_FFF

64 bytes

 

 

 

001

$_F80-$_FFF

128 bytes

 

 

 

010

$_F40-$_FFF

192 bytes

 

 

 

011

$_F00-$_FFF

256 bytes

 

 

 

100

$_EC0-$_FFF

320 bytes

 

 

 

101

$_E80-$_FFF

384 bytes

 

 

 

110

$_E40-$_FFF

448 bytes

 

 

 

111

$_E00-$_FFF

512 bytes

 

 

 

3.3.6 ESTAT — EEPROM Status Register

The ESTAT register defines the operational status of the module.

Address Offset: $_05

 

7

6

5

4

3

2

1

0

R

CBEIF

CCIF

PVIOL

ACCERR

0

BLANK

0

0

W

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset:

1

1

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 3-7 EEPROM Status Register (ESTAT)

CBEIF, PVIOL and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read zero and are not writable.

CBEIF — Command Buffer Empty Interrupt Flag.

The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a “1” to CBEIF. Writing a “0” to the CBEIF flag has no effect on CBEIF. Writing a “0” to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set. Writing a “0” to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request (see Figure 4-8).

1 = Buffers are ready to accept a new command.

0 = Buffers are full.

CCIF — Command Complete Interrupt Flag.

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Contents Freescale Semiconductor, Inc Original Release Date 7 JUL Revised 30 OCT Motorola, IncRevision History Table of Contents Freescale Semiconductor, Inc List of Figures Freescale Semiconductor, Inc List of Tables Freescale Semiconductor, Inc Freescale Semiconductor, Inc Freescale Semiconductor, Inc Features IntroductionOverview Modes of OperationBlock Diagram InterfaceClock DividerExternal Signal Description Eeprom Configuration Field Memory Map and RegistersModule Memory Map Eeprom Memory Map Address Register Name Normal Mode Offset Access Eeprom Register MapRegister Descriptions Eclkdiv Eeprom Clock Divider RegisterEcnfg Eeprom Configuration Register RESERVED2Eprot Eeprom Protection Register Eeprom Protection Register EprotEstat Eeprom Status Register Eeprom Protection Address RangeEcmd Eeprom Command Register Eeprom Command Register Ecmd Valid Eeprom Command ListEaddr Eeprom Address Registers Edata Eeprom Data Registers13 Eeprom Data Low Register Edatalo Writing the Eclkdiv Register Eeprom Command OperationsFunctional Description 200 -182 ⁄ 200 × 100 = 9% Determination Procedure for PRDIV8 and Ediv Bits Eeprom Command Description Command Write SequenceEeprom Commands Erase Verify Command SectorExample Erase Verify Command Flow Program Command Freescale Semiconductor, Inc Example Program Command Flow Sector Erase Command Freescale Semiconductor, Inc Example Sector Erase Command Flow Mass Erase Command Example Mass Erase Command Flow Sector Erase Abort Command Freescale Semiconductor, Inc Ccif Example Sector Modify Command Flow Illegal Eeprom Operations3.5 Wait Mode Stop ModeBackground Debug Mode Unsecuring the MCU in Special Single Chip Mode via the BDMResets Eeprom Reset SequenceReset While Eeprom Command Active InterruptsEeprom Interrupt Implementation Index Freescale Semiconductor, Inc Block Guide End Sheet Final Pages

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