Finisar FTLX8561E2 manual Pin Descriptions, Transmit Functions

FTLX8561E2 Product Specification – October 2008

I. Pin Descriptions

Signal Name	Level	I/O	Pin No.	Description
Management and	Monitoring Ports
MDIO	Open Drain	I/O	17	Management Data I/O. Requires
				external 10 - 22 kΩ pull-up to the
				APS on host.
MDC	1.2 V	I	18	Management Data Clock Input
	CMOS
PRTAD4	1.2 V	1	19	Port Address Input bit 4
	CMOS
PRTAD3	1.2 V	I	20	Port Address Input bit 3
	CMOS
PRTAD2	1.2 V	I	21	Port Address Input bit 2
	CMOS
PRTAD1	1.2 V	I	22	Port Address Input bit 1
	CMOS
PRTAD0	1.2 V	I	23	Port Address Input bit 0
	CMOS
LASI	Open Drain	O	9	Link Alarm Status Interrupt Output.
				Open Drain Compatible Output with
				10 - 20 kΩ pull-up on host.
				Logic high = Normal Operation
				Logic low = Status Flag Triggered
RESET	Open Drain	I	10	Reset Input.
				Open Drain Compatible Input with
				22 kΩ pull-up to APS internal to
				transponder.
				Logic high = Normal Operation
				Logic low = RESET
Vendor Specific			11,15,16,24	Vendor Specific Pins.
				Leave unconnected when not used.
TX ON/OFF	Open Drain	I	12	TX ON/OFF Input.
				Open Drain Compatible Input with
				22 kΩ pull-up to APS internal to
				transponder.
				Logic high = Transmitter On
				Logic low = Transmitter Off
MOD DETECT		O	14	Pulled low inside transponder
				through a 1 kΩ resistor to Ground
Transmit Functions
Reserved		I	68	Reserved For Future Use
Reserved		I	67	Reserved For Future Use
TX LANE 3–	AC-coupled,	I	65	Module XAUI Input Lane 3–
TX LANE 3+	Internally biased	I	64	Module XAUI Input Lane 3+
	differential
TX LANE 2–		I	62	Module XAUI Input Lane 2–
	XAUI
TX LANE 2+		I	61	Module XAUI Input Lane 2+
TX LANE 1–		I	59	Module XAUI Input Lane 1–
TX LANE 1+		I	58	Module XAUI Input Lane 1+
TX LANE 0–		I	56	Module XAUI Input Lane 0–
TX LANE 0+		I	55	Module XAUI Input Lane 0+

© Finisar Corporation – October 2008 Rev B Page 2