Cypress CY25822-2 manual Bytes 2 through 5 Reserved Registers, PWRDWN# Power-down Clarification

Page 4

 

 

 

 

 

 

 

 

 

 

CY25822-2

 

 

 

 

 

 

 

 

 

 

 

 

Table 4. Spread Spectrum Select (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS3

SS2

SS1

SS0

 

Spread Mode

 

Spread Amount%

 

 

 

 

 

 

 

 

 

 

 

0

 

1

0

1

 

Down

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

1

0

 

Down

 

2.5

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

1

1

 

Down

 

3.0

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

0

0

 

Center

 

±0.3

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

0

1

 

Center

 

±0.4

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

1

0

 

Center

 

±0.5

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

1

1

 

Center

 

±0.6

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

0

0

 

Center

 

±0.8

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

0

1

 

Center

 

±1.0

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

1

0

 

Center

 

±1.25

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

1

1

 

Center

 

±1.5

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 1: Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

@Pup

Pin#

Name

 

 

Pin Description

 

 

 

 

 

 

 

 

 

7

 

1

5

REFEN

 

REFOUT enable

 

 

 

 

 

 

 

 

 

 

0 = disabled, 1 = enabled

 

 

 

 

 

 

 

 

 

6

 

1

5

REFSLEW

 

REFOUT edge rate control

 

 

 

 

 

 

 

 

0 = slow, 1 = nominal

 

 

 

 

 

 

 

 

 

 

 

 

5

 

0

 

 

Not Applicable

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

4

 

0

 

 

Not Applicable

 

Reserved

 

 

 

 

 

 

 

 

 

3

 

1

4

CLKSLEW

 

CLKOUT edge rate control

 

 

 

 

 

 

 

 

0 = slow, 1 = nominal

 

 

 

 

 

 

 

 

 

 

 

2

 

1

4

CLKEN

 

CLKOUT enable

 

 

 

 

 

 

 

 

 

 

0 =disabled, 1 = enabled

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

 

Not Applicable

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

 

Not Applicable

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bytes 2 through 5: Reserved Registers

Byte 6: Vendor/Revision ID Register

Bit

@Pup

Pin#

Name

Pin Description

 

 

 

 

 

7

0

Revision ID Bit 3

 

 

 

 

 

6

0

Revision ID Bit 2

 

 

 

 

 

5

0

Revision ID Bit 1

 

 

 

 

 

4

0

Revision ID Bit 0

 

 

 

 

 

3

1

Vendor ID Bit 3

 

 

 

 

 

2

0

Vendor ID Bit 2

 

 

 

 

 

1

0

Vendor ID Bit 1

 

 

 

 

 

0

0

Vendor ID Bit 0

 

 

 

 

 

PWRDWN# (Power-down) Clarification

The PWRDWN# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PWRDWN# is an asynchronous active LOW input. This signal is synchro- nized internally to the device powering down the clock synthe- sizer. PWRDWN# is an asynchronous function for powering up the system. When PWRDWN# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. When PWRDWN# is deasserted the clocks should remain stopped until the VCO is stable and

within specification (tSTABLE). A stopped clock is either tri-stated or driven low depending on the state of the tri-state

enable I2C register bit. CY25822 clocks that are stopped in the driven state are driven low.

The CLKIN input must be on and within specified operating parameters before PWRDWN# is asserted and it must remain in this state while PWRDWN# is asserted.

Document #: 38-07531 Rev. **

Page 4 of 9

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Contents Features Block DiagramPin Configuration 2 5 8 2 2Serial Data Interface Pin DescriptionData Protocol Spread Mode Spread Amount% Block Read and Block Write ProtocolByte 0 Control Register Bit @Pup Pin# Name Pin Description Spread Spectrum SelectBytes 2 through 5 Reserved Registers PWRDWN# Power-down ClarificationByte 1 Control Register Bit @Pup Pin# Name Pin Description Clkout and Refout Enable Clarification Power-down AssertionParameter Description Condition Min Max Unit Description Conditions Min Max UnitOrdering Information Signal Loading Table Clock Name Max Load pFPart Number Package Type Product Flow Package Diagram Lead 150-Mil Soic S8Document History New Data SheetDate Change Description of Change 124462

CY25822-2 specifications

The Cypress CY25822-2 is a highly versatile clock generator and clock distribution device designed for use in high-performance applications. As part of Cypress's extensive portfolio of timing solutions, the CY25822-2 takes center stage in delivering precise clock signals for system synchronization and performance enhancement.

One of the standout features of the CY25822-2 is its ability to generate multiple output clocks from a single input source. This functionality is particularly beneficial in applications where multiple components or subsystems require synchronized clock signals, allowing designers to simplify their designs and reduce component count.

The CY25822-2 supports a wide input frequency range, accommodating various system clock sources while maintaining low jitter performance. This characteristic is critical in high-speed digital applications, where timing precision is paramount. With its ability to minimize phase noise and jitter, the CY25822-2 ensures reliable data transmission and system stability.

Another notable aspect of the CY25822-2 is its programmable features. The device can be configured through a simple interface, allowing designers to customize the output frequencies and clock characteristics according to their specific application needs. This programmability enhances flexibility, enabling the CY25822-2 to be used in diverse environments, from consumer electronics to automotive systems.

The CY25822-2 utilizes advanced phase-locked loop (PLL) technology to achieve high-performance clock generation. The PLL feature allows it to multiply input frequencies and generate higher frequency outputs while maintaining excellent signal integrity. This capability is crucial for modern high-speed data applications, including networking, telecommunications, and high-definition video processing.

In terms of power efficiency, the CY25822-2 is designed to operate with low power consumption, making it suitable for battery-operated devices and energy-sensitive applications. The reduced power footprint contributes to prolonged battery life and better overall system performance.

Moreover, the CY25822-2 package options cater to various design requirements, offering flexibility for integration into a range of PCB layouts. Its small footprint suits compact devices, while its robust operation ensures reliability across different environmental conditions.

In conclusion, the Cypress CY25822-2 stands out as a reliable and advanced clock generator solution, integrating essential features such as multiple outputs, low jitter performance, programmability, and power efficiency. Its adoption across various high-performance applications underscores its importance in the modern electronics landscape.