Cypress CY62128B manual Product Portfolio, Pin Configurations, Pin Definitions, Soic

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CY62128B

MoBL®

Product Portfolio

 

 

 

 

 

 

 

 

Power Dissipation

 

 

 

 

 

 

 

 

Operating, ICC

Standby, ISB2

 

 

 

VCC Range (V)

 

Speed

(mA)

(µA)

 

Product

Min.

Typ.[2]

 

Max.

(ns)

Typ.[2]

Max.

Typ.[2]

 

Max.

CY62128BLL

Industrial

4.5

5.0

 

5.5

55

7.5

20

2.5

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

Industrial

 

 

 

 

70

6

15

2.5

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

Automotive

 

 

 

 

70

6

25

2.5

 

25

 

 

 

 

 

 

 

 

 

 

 

 

Pin Configurations

Top View

 

SOIC

 

NC

1

32

VCC

A16

2

31

A

A14

3

30

15

CE

A12

4

29

2

WE

A7

5

28

A13

A6

6

27

A8

A5

7

26

A

A4

8

25

9

A

A3

9

24

11

OE

A2

10

23

A10

A1

11

22

CE

 

 

1

A0

12

21

I/O7

I/O0

13

20

I/O6

I/O1

14

19

I/O5

I/O2

15

18

I/O4

GND 16

17

I/O3

 

A4

 

 

 

16

 

 

 

A

A11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

 

 

 

 

17

 

3

 

 

25

 

24

 

 

OE

A11

 

1

 

32

 

 

OE

 

 

 

15

 

18

 

A

A

 

 

26

 

23

 

 

A10

 

A9

 

2

 

31

 

 

A10

 

 

A6

 

 

 

 

 

2

9

 

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

19

 

A1

A8

 

 

 

22

 

 

CE1

A

 

3

 

30

 

 

CE

 

A7

 

 

13

 

20

 

A0

A13

 

 

28

 

21

 

 

I/O7

A 8

 

4

 

29

 

 

I/O

1

A

 

 

12

 

21

 

I/O

WE

 

 

29

 

20

 

 

I/O

13

 

5

 

28

 

 

 

7

A12

 

 

11

 

 

 

I/O0

CE

 

 

30

 

19

 

 

I/O6

WE

 

 

 

 

I/O6

 

 

 

 

 

6

 

 

 

A 14

 

 

10

Reverse TSOP I

22

 

I/O1

A152

 

 

31

STSOP

18

 

 

I/O5

CE2

 

 

27

 

 

I/O5

 

 

 

 

 

 

16

 

 

 

 

Top View

23

 

2

VCC

 

 

32

Top View

17

 

4

A15

 

7

TSOP I

26

 

 

I/O

4

NC

 

 

9

24

 

GND

 

 

 

 

I/O3

VCC

 

8

Top View

25

 

 

 

V

 

 

 

 

 

(not to scale)

 

 

I/O

NC

 

 

1

(not to scale)

16

 

 

GND

 

24

 

 

I/O3

 

CC

 

 

8

 

25

 

I/O3

A16

 

 

2

 

15

 

 

I/O2

NC

 

9

(not to scale)

 

 

GND

A15

 

 

7

 

26

 

I/O4

A

 

 

3

 

14

 

 

I/O1

A16

 

10

 

23

 

 

I/O2

CE2

 

 

6

 

27

 

I/O5

A1214

 

 

4

 

13

 

 

I/O0

A14

 

11

 

22

 

 

I/O1

WE

 

 

5

 

28

 

6

A

 

 

5

 

12

 

 

A

A12

 

12

 

21

 

 

I/O0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A13

 

 

4

 

29

 

I/O7

A7

 

 

6

 

11

 

 

A10

A7

 

13

 

20

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

3

 

30

 

CE1

A6

 

7

 

10

 

 

A2

A6

 

14

 

19

 

 

A1

 

 

 

 

 

 

 

 

A10

 

 

 

 

18

 

 

 

 

A9

 

 

2

 

31

 

A5

 

8

 

9

 

 

A3

A5

 

15

 

 

 

A2

 

A11

 

 

 

1

 

32

 

OE

4

 

 

 

 

 

 

 

 

 

A4

 

16

 

17

 

 

A3

 

Pin Definitions

Input

 

A0-A16. Address Inputs

Input/Output

 

I/O0-I/O7. Data lines. Used as input or output lines depending on operation

Input/Control

 

 

 

 

. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ

 

WE

 

 

is conducted.

Input/Control

 

 

1. Chip Enable 1, Active LOW.

 

CE

Input/Control

 

CE2. Chip Enable 2, Active HIGH.

Input/Control

 

 

 

. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as

 

OE

 

 

outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins

Ground

 

GND. Ground for the device

 

 

 

Power Supply

 

VCC. Power supply for the device

Note:

2.Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25°C, and tAA = 70 ns.

Document #: 38-05300 Rev. *C

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Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor CorporationPin Definitions Pin ConfigurationsProduct Portfolio SoicMaximum Ratings Electrical Characteristics Over the Operating RangeRange Ambient Temperature T Operating RangeAC Test Loads and Waveforms Thermal Resistance6Capacitance6 Data Retention WaveformRead Cycle Switching Characteristics7 Over the Operating RangeSwitching Waveforms Write CycleRead Cycle No OE Controlled13 Write Cycle No CE1 or CE2 Controlled15Data I/O Data Invalid Write Cycle No WE Controlled, OE High During Write15Write Cycle No.3 WE Controlled, OE LOW15 DATAI/O Data ValidOrdering Information 0-I/O Mode PowerTruth Table Lead Thin Small Outline Package Type I 8x20 mm Z32 Package DiagramsLead 450 MIL Molded Soic S34 Lead Shrunk Thin Small Outline Package 8x13.4 mm ZA32 Lead Reverse Thin Small Outline Package ZR32REV ECN no Issue Orig. Description of Change DateDocument History

CY62128B specifications

The Cypress CY62128B is a high-performance static random-access memory (SRAM) device designed to deliver reliable data storage solutions in a variety of applications. This device is particularly notable for its speed and high-density capabilities, making it suitable for both consumer electronics and industrial applications.

One of the main features of the CY62128B is its organization as a 128K-bit memory chip, which typically comes in a 16K x 8-bit configuration. This allows for efficient processing and storage of data, enabling quick access times. The device boasts access times of 55 ns, making it an excellent choice for applications that require fast data retrieval and processing. Such speed is crucial for modern computing tasks, where delays can significantly impact overall performance.

In addition to its speed, the CY62128B incorporates low-power consumption technology, which is vital for battery-operated devices and other energy-sensitive applications. The operating current is typically in the range of 30 mA, while the standby current is a mere 0.02 mA when the chip is not in use. This combination of low power and high-speed functionality ensures that the device operates efficiently in a wide range of conditions.

The CY62128B also features a wide operating voltage range, accommodating both 2.7V to 5.5V. This versatility allows it to be employed in diverse environments and devices, adapting as necessary to various power supply configurations. Its compatibility with different voltage levels enhances its usability in portable electronics and various embedded systems.

Additionally, the CY62128B benefits from a fast transition between read and write operations, thanks to its asynchronous memory structure. This means that data can be changed and accessed without the need for complex timing sequences, promoting simplicity in system design and reducing overhead.

Another significant characteristic is the robust reliability of the CY62128B, which uses advanced CMOS technology. The chip is built to withstand challenging operating conditions, such as extreme temperatures and radiation exposure, making it suitable for aerospace and military applications.

In summary, the Cypress CY62128B is a versatile and reliable SRAM solution, offering high density, fast access times, low power consumption, and a broad operating voltage range. These features make it an ideal choice for diverse applications, from consumer electronics to industrial systems. Its combination of speed, efficiency, and reliability reflects the innovation that Cypress is known for in the semiconductor industry.