Cypress CY62128B manual Switching Characteristics7 Over the Operating Range, Switching Waveforms

CY62128B

MoBL®

Switching Characteristics[7] Over the Operating Range

					62128B-55		62128B-70
Parameter				Description					Unit
					Min.	Max.	Min.	Max.
READ CYCLE
tRC		Read Cycle Time			55		70		ns
tAA		Address to Data Valid				55		70	ns
tOHA		Data Hold from Address Change			5		5		ns
tACE			1 LOW to Data Valid, CE2 HIGH to Data Valid			55		70	ns
		CE
tDOE				LOW to Data Valid		20		35	ns
		OE
tLZOE				LOW to Low Z	0		0		ns
		OE
tHZOE				HIGH to High Z[7, 9]		20		25	ns
		OE
tLZCE			1 LOW to Low Z, CE2 HIGH to Low Z[9]		5		5		ns
		CE
tHZCE			1 HIGH to High Z, CE2 LOW to High Z[8, 9]			20		25	ns
		CE
tPU			1 LOW to Power-up, CE2 HIGH to Power-up		0		0		ns
		CE
tPD			1 HIGH to Power-down, CE2 LOW to Power-down			55		70	ns
		CE
WRITE CYCLE	[10]
tWC		Write Cycle Time			55		70		ns
tSCE			1 LOW to Write End, CE2 HIGH to Write End		45		60		ns
		CE
tAW		Address Set-up to Write End			45		60		ns
tHA		Address Hold from Write End			0		0		ns
tSA		Address Set-up to Write Start			0		0		ns
tPWE				Pulse Width	45		50		ns
		WE
tSD		Data Set-up to Write End			25		30		ns
tHD		Data Hold from Write End			0		0		ns
tLZWE				HIGH to Low Z[9]	5		5		ns
		WE
tHZWE				LOW to High Z[8, 9]		20		25	ns
		WE

Switching Waveforms

Read Cycle No.1[12, 13]

ADDRESS				tRC
			tAA
DATA OUT		tOHA
	PREVIOUS DATA VALID				DATA VALID

Notes:

7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance.

8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

11. No input may exceed VCC + 0.5V.

12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

13. WE is HIGH for read cycle.

Document #: 38-05300 Rev. *C Page 5 of 11

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