Cypress CY7C1231H manual NOP, Stall and Deselect Cycles18, 19, ZZ Mode Timing22

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CY7C1231H

Switching Waveforms (continued)

NOP, STALL and Deselect Cycles[18, 19, 21]

CLK

CEN

CE

ADV/LD

WE

BW[A:B]

ADDRESS

DQ

COMMAND

1

2

3

4

5

A1 A2 A3 A4

 

D(A1)

 

Q(A2)

Q(A3)

WRITE

READ

STALL

READ

WRITE

D(A1)

Q(A2)

 

Q(A3)

D(A4)

6

7

8

9

10

A5

tCHZ

D(A4) Q(A5)

 

 

 

tDOH

STALL

NOP

READ

DESELECT CONTINUE

 

 

Q(A5)

DESELECT

DON’T CARE

UNDEFINED

ZZ Mode Timing[22, 23]

CLK

ZZ

ISUPPLY

ALL INPUTS (except ZZ)

Outputs (Q)

tZZ

t ZZI

I DDZZ

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.

23.I/Os are in tri-state when exiting ZZ sleep mode.

Document #: 001-00207 Rev. *B

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Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor CorporationCY7C1231H Pin ConfigurationSelection Guide 133 MHz UnitPin Definitions Sleep Mode Functional OverviewLinear Burst Address Table Mode = GND Truth Table for Read/Write 2Operating Range Maximum RatingsAmbient Range Thermal Resistance11 Capacitance11AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 12 Command Switching WaveformsRead/Write Waveforms 18, 19 ZZ Mode Timing22 NOP, Stall and Deselect Cycles18, 19Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm PCI Issue Date Orig. Description of ChangeDocument History NXR