Cypress CY7C1019CV33 manual Switching Waveforms, Read Cycle No OE Controlled 12

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CY7C1019CV33

Switching Waveforms

Read Cycle No. 1[11, 12]

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
		tRC
CE
	tACE
OE		tHZOE
	tDOE	tHZOE
	tDOE	tHZCE
	tLZOE	tHZCE	HIGH
DATA OUT	HIGH IMPEDANCE	DATA VALID	IMPEDANCE
DATA OUT		DATA VALID
	tLZCE	tPD
VCC	tPU	tPD	ICC
SUPPLY	50%		50%
CURRENT			ISB

Write Cycle No. 1 (CE Controlled)[14, 15]

		tWC
	ADDRESS
		tSCE
	CE
	tSA
	tAW	tSCE	tHA
	tAW	tPWE	tHA
		tPWE
	WE
		tSD	tHD
	DATA I/O	DATA VALID

Notes:

11.Device is continuously selected. OE, CE = VIL.

12.WE is HIGH for read cycle.

13.Address valid prior to or coincident with CE transition LOW.

14.Data I/O is high impedance if OE = VIH.

15.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Document #: 38-05130 Rev. *F

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Contents Logic Block Diagram FeaturesPin Configuration Functional DescriptionUnit Pin Configuration1 Selection GuideBall Vfbga Top View Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Capacitance3AC Test Loads and Waveforms4 Switching Characteristics Over the Operating Range5Parameter Description Unit Min Max Read Cycle Write Cycle 9Read Cycle No Switching WaveformsRead Cycle No OE Controlled 12 Write Cycle No CE Controlled14Truth Table 0-I/O Mode PowerWrite Cycle No WE Controlled, OE High During Write14 Write Cycle No WE Controlled, OE LOW15Pin 400-Mil Molded SOJ Package DiagramsOrdering Information Pin Tsop II Ball Vfbga 6 x 8 x 1 mm Document History Issue Orig. Description of Change Date