CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
■Pin and function compatible with CY7C1041CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA at 10 ns (industrial)
■Low CMOS standby power
❐ISB2 = 10 mA
■2.0V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in
Functional Description
The CY7C1041DV33[1] is a high performance CMOS Static RAM organized as 256K words by 16 bits. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from IO pins (IO0 to IO7) is written into the location specified on the address pins (A0 to A17). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO8 to IO15) is written into the location specified on the address pins (A0 to A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of read and write modes.
The input and output pins (IO0 to IO15) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).
The CY7C1041DV33 is available in a standard
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
256K × 16
COLUMN
DECODER
9 | 10 | 11 12 13 14 15 16 | 17 |
A A A A A A A A A | |||
SENSE AMPS
IO0–IO7
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document #: |
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| Revised July 17, 2008 | |
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