Cypress CY7C1020BN manual Features, Functional Description, Logic Block Diagram Pin Configuration

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Features

•High speed

—tAA = 12, 15 ns

•CMOS for optimum speed/power

•Low active power

—825 mW (max.)

•Low CMOS standby power (L version only)

—2.75 mW (max.)

•Automatic power-down when deselected

•Independent control of upper and lower bits

•Available in 44-pin TSOP II and 400-mil SOJ

CY7C1020BN

32K x 16 Static RAM

Functional Description

The CY7C1020BN is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

The CY7C1020BN is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages.

Logic Block Diagram

Pin Configuration

DATA IN DRIVERS

SOJ / TSOP II

Top View

A7 A6 A5 A4 A3 A2 A1 A0

ROW DECODER

32K x 16

 

AMPS

 

 

 

 

 

 

 

 

 

 

 

RAM Array

 

SENSE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O1–I/O8

I/O9–I/O16

NC A3 A2 A1

A0

CE

I/O1

I/O2

I/O3

I/O4

VCC

VSS

I/O5

I/O6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

44

43

42

41

40

39

38

37

36

35

34

33

32

31

A5

A6

A7 OE

BHE

BLE

I/O16

I/O15

I/O14

I/O13

VSS

VCC

I/O12

I/O11

COLUMN DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

9

10

11

12

13

14

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

A A A A A A A

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O7 I/O8

WE

A15

A14

A13

A12

NC

15

16

17

18

19

20

21

22

30

29

28

27

26

25

24

23

I/O10

I/O9

NC

A8

A9

A10

A11

NC

Cypress Semiconductor Corporation

•

198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 001-06443 Rev. **

 

Revised February 1, 2006

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Contents Logic Block Diagram Pin Configuration FeaturesFunctional Description Cypress Semiconductor CorporationSelection Guide Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance4AC Test Loads and Waveforms Switching Characteristics5 Over the Operating RangeWrite Cycle Read Cycle No Switching WaveformsRead Cycle No OE Controlled 10 Write Cycle No BLE or BHE Controlled Write Cycle No CE Controlled12Truth Table 1-I/O 9-I/O Mode PowerOrdering Information Write Cycle No WE Controlled, OE LOWLead 400-Mil Molded SOJ Package DiagramsPin Tsop II New Data Sheet Issue Orig. Description of Change Date 426812 See ECNDocument History Document Title CY7C1020BN 32K x 16 Static RAM Document #

CY7C1020BN specifications

The Cypress CY7C1020BN is a high-performance SRAM (Static Random Access Memory) device that is particularly well-suited for high-speed applications requiring fast access times and low power consumption. This 1 Megabit (1Mbit) SRAM is organized as 128K words by 8 bits, providing a total storage capacity that is ideal for embedded systems, networking equipment, and other devices that demand rapid data processing capabilities.

One of the standout features of the CY7C1020BN is its access time of 10 ns to 15 ns, allowing for swift data read and write operations. This speed is critical in environments where timing is essential, such as telecommunications and computing applications. The device fully supports asynchronous read and write cycles, leading to efficient performance without the need for complex control logic.

The CY7C1020BN utilizes a CMOS (Complementary Metal-Oxide-Semiconductor) technology which contributes to its low power consumption profile. It operates at a voltage of 2.7V to 5.5V, making it versatile for various system designs. The device boasts a low standby current of 1 µA, a significant advantage in battery-operated applications where power savings are crucial.

Additionally, the CY7C1020BN is designed for ease of use, featuring simple interfacing options that allow for seamless integration into existing designs. It operates using standard asynchronous control signals, making it compatible with a wide range of microcontrollers and FPGAs.

In terms of reliability, the CY7C1020BN is built to endure various environmental conditions and has a solid reputation for robust performance over time. Features such as an extended temperature range and guaranteed write endurance enhance its durability in demanding applications.

The package options for the CY7C1020BN include various pin configurations, accommodating different board layouts and space constraints. This flexibility makes it an attractive choice for designers seeking to optimize their space without compromising on performance.

In summary, the Cypress CY7C1020BN is an excellent choice for applications requiring high-speed, low-power static RAM. With its fast access times, low power consumption, versatile voltage range, and compatibility with standard control signals, it continues to be a preferred memory solution in various high-performance systems. Whether in communication devices, industrial equipment, or consumer electronics, it provides reliability and efficiency that engineers can count on.
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