Cypress CY62148ESL manual Features, Functional Description, Logic Block Diagram

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Features

Very high speed: 55 ns

Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V

Ultra low standby power

Typical standby current: 1 μA

Maximum standby current: 7 μA

Ultra low active power

Typical active current: 2 mA at f = 1 MHz

Easy memory expansion with CE and OE features

Automatic power down when deselected

CMOS for optimum speed and power

Available in Pb-free 32-pin STSOP package

CY62148ESL MoBL®

4-Mbit (512K x 8) Static RAM

Functional Description

The CY62148ESL is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW).

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18).

To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Logic Block Diagram

 

 

 

 

 

 

 

 

A0

 

INPUT BUFFER

 

 

IO0

A1

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

IO1

A3

DECODER

 

512K x 8

 

 

AMPS

A6

 

 

 

IO3

A4

 

 

 

 

 

 

 

IO2

A5

 

 

 

 

 

 

 

 

A7

ROW

 

 

 

 

 

SENSE

 

A8

 

ARRAY

 

 

IO4

A9

 

 

 

 

 

 

 

 

A10

 

 

 

 

 

 

 

IO5

A11

 

 

 

 

 

 

 

 

A12

 

 

 

 

 

 

 

IO6

CE

COLUMN DECODER

POWER

IO7

WE

 

 

 

 

 

 

DOWN

 

OE

13

14

15

16

17

18

 

 

 

 

 

 

A

A

A

A

A

A

 

 

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 001-50045 Rev. **

 

Revised January 21, 2009

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtProduct Portfolio Pin ConfigurationMaximum Ratings Electrical CharacteristicsOperating Range Device Range AmbientThermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test ConditionsData Retention Waveform Data Retention CharacteristicsParameter Description Conditions Min Typ Max Unit Parameter Read Cycle Description 55 ns Min Max Unit Switching CharacteristicsWrite Cycle Read Cycle No OE Controlled 14 Switching WaveformsTruth Table Inputs/Outputs Mode PowerOrdering Information Package Diagram51-85094 Pin Stsop Pb-Free New data sheet Sales, Solutions, and Legal InformationDocument History