Cypress CY7C656xx, EZ-USB HX2LP manual Features, Introduction, Cypress Semiconductor Corporation

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PRELIMINARYCY7C656xx

EZ-USB HX2LP™

Low-Power USB 2.0 Hub Controller Family

1.0Features

USB 2.0 hub controller

Compliant with the USB 2.0 specification

WindowsHardware-quality lab (WHQL)-compliant

Up to four downstream ports supported

Supports bus-power and self powered modes

Single-TT and Multi-TT modes supported

Single-TT option for low-cost

Multi-TT option for high performance

2-Port

Single TT option for bus power

Fit/form/function compatible option with CY7C65640 (TetraHub)

Multiple package options

Space-saving 56 QFN

Single power supply requirement

Internal regulator for reduced cost

Integrated upstream pull-up resistor

Integrated pull-down resistors for all downstream ports

Integrated upstream and downstream termination resistors

Integrated port status indicator controls

24-MHz external crystal (integrated PLL)

Configurable with external SPI EEPROM

Vendor ID, Product ID, Device ID (VID/PID/DID)

Number of active ports

Number of removable ports

Maximum power setting for high-speed and full- speed

Hub controller power setting

Power-on timer

Overcurrent detection mode

Overcurrent timer

Enable/Disable overcurrent timer

Overcurrent pin polarity

indicator pin polarity

Compound device

Enable full-speed only

Disable port indicators

Gang power switching

Enable single-TT mode only

Self/bus powered compatibility

Fully configurable string descriptors for multiple language support

In-system EEPROM programming

2.0Introduction

EZ-USB HX2LPis Cypress’s next-generation family of high- performance, low-power USB 2.0 hub controllers. HX2LP is an ultra low-power single-chip USB 2.0 hub controller with integrated upstream and downstream transceivers, a USB Serial Interface Engine (SIE), USB Hub Control and Repeater logic, and Transaction Translator (TT) logic. Cypress has also integrated many of the external passive components, such as pull-up and pull-down resistors, reducing the overall bill-of- materials required to implement a hub design. The entire HX2LP portfolio consists of:

1.CY7C65640B (TetraHub LP): 4-port/multiple transaction translator

This device option is fit/form/function compatible with Cy- press’s existing CY7C65640 device. Cypress’s “Tetra” ar- chitecture provides four downstream USB ports, each with a dedicated Transaction Translator (TT), making it the high- est-performance hub available. The TetraHub LP also of- fers best-in-class power consumption. The CY7C65640B is available in a 56 QFN (TetraHub pin-compatible) for space saving designs.

2.CY7C65630: 4-port/single transaction translator

This device option is for ultra low-cost applications where performance is secondary consideration. All four ports must share a single transaction translator in this configura- tion. The CY7C65630 is available in a 56 QFN and is also pin for pin-compatible with the CY7C65640.

3.CY7C65620:

This device option is for a 2-port bus powered application. Both ports must share a single transaction translator in this configuration. The CY7C65620 is available in a 56 QFN and is also pin for pin compatible with the CY7C65640.

All device options are supported by Cypress’s world-class reference design kits, which include board schematics, bill of materials, Gerber files, Orcad files, and thorough design documentation.

Cypress Semiconductor Corporation

3901 North First Street

San Jose , CA 95134

408-943-2600

Document #: 38-08037 Rev. *D

 

 

 

Revised March 31, 2005

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Contents Introduction FeaturesCypress Semiconductor Corporation CY7C65640B Block Diagram Block DiagramsCY7C65630/CY7C65620 Block Diagram Functional Overview ApplicationsPort Indicators Power SwitchingUpstream Port Over-current DetectionPort Indicator Color Definitions in Manual Mode Port State Pin Quad Flat Pack No Leads 8 mm x 8 mm2 Pin ConfigurationPin Description Table Downstream D+ Signal Downstream D- SignalOvercurrent Condition Detection Input. Default is Active Configuration Descriptor Default DescriptorsDevice Descriptor Interface DescriptorInterface Descriptor9,10 Endpoint DescriptorEndpoint Descriptor9,10 Device Qualifier DescriptorDefault 0xD0 Load Configuration OptionsHub Descriptor Byte All Speed Field Name DescriptionConfigured 0xD4 Load Configured 0xD2 LoadByte 9 MaximumPower High-Speed Byte 8 MaximumPower Full-SpeedByte 12 HubControllerPower Full-Speed Byte 13 HubControllerPower High-speedByte 21 SupportedStrings Byte 19 Write Protect Byte 20 NumLangsBit Name Supported USB Requests Device Class CommandsPortindicator Hub Class CommandsPorttest Hub Class Feature Selector Recipient Value Vendor CommandsDownstream USB Connections Upstream USB ConnectionLED Connections Sample Schematic System Block DiagramElectrical Characteristics 16.0 Ordering Information 17.0 Package DiagramsOrdering Code Package Type CY46XXDocument History Issue Date Change Description of ChangeJTC KKU