PRELIMINARYCY7C656xx
3.0Block Diagrams
24
MHz
Cry s tal
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| U SB 2.0 PH Y |
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| Serial |
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| USB C ontrol Logic |
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| PLL |
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| Interface |
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| S PI_SCK |
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| Engine |
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| SPI Com m unication | ||||
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| S PI_SD | |||||
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| Block | ||
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| U SB Upstream Port |
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| S PI_CS | |||
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| Transaction Translator (X4) |
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| H ub Repeater |
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| TT RAM |
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| Routing Logic |
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| U SB Downstream Port 1 |
| USB D ownstream Port 2 |
| USB D ow nstream Port 3 |
| USB D ow nstream Port 4 | ||||||||
US B 2.0 Port P ower | Port | USB 2.0 Port P ower | Port | USB 2.0 | Port P ower | Port | USB 2.0 P ort P ower | Port | |||||||
| P HY | Control | S tatus |
| PHY | Control | S tatus |
| PHY | Control | S tatus |
| PHY | Control | S tatus |
D+ | D- | P W R#[1] | LE D | D+ | D- | P W R#[2] | LE D | D+ | D- | P W R#[3] | LE D | D+ | D- | P W R#[4] | LE D |
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| OVR#[1] |
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| OVR#[2] |
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| OV R#[3] |
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| OVR#[4] | ||||
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| Figure |
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Document #: | Page 2 of 23 |