MCU_PORT 2
PK0
PK2
PK4
PB0/D0
PB2/D2
PB4/D4
PB6/D6
PE0/XIRQ*
PE6/MODB
A14
A15
A16
A17
1 | 2 | PK1 |
3 | 4 | PK3 |
5 | 6 | PK5 |
7 | 8 | PK7/ECS |
9 | 10 | PB1/D1 |
11 | 12 | PB3/D3 |
13 | 14 | PB5/D5 |
15 | 16 | PB7/D7 |
17 | 18 | PE3/LSTRB* |
19 | 20 | PE5/MODA |
21 | 22 | PE7 |
23 | 24 | A18 |
25 | 26 | A19 |
The MCU_PORT 2 provides access to the Expanded Bus and I/O lines of the HC12. Note:
1)Not all I/O Ports are provided by all HC12 MCUs.
2)The A14 - A19 address signals are provided by the PRU. The A16 - A19 signals are derived from the HC12 PK0 - PK5 signals when emulating internal flash paging operation.
BUS_PORT
GND D10 D9 D8 A0 A1 A10
/OE A11 A9 A8 A12
/WE CS1 CS3 CS5 +5V /RW
E GND
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
D11
D12
D13
D14
D15
A2
A3
A4
A5
A6
A7
A13
CS0
CS2
CS4
/ RESET
The BUS_PORT supports
D8 - D15 High Byte Data Bus in Wide Expanded Mode and Peripheral 8 bit data bus. Port A in Single Chip Mode.
A0 – A13 Memory Addresses 0 to 13.
/OE Memory Output Enable signal, Active Low. Valid with ECLK and R/W high.
CS0 – CS7 Peripheral chip selects, 16 bytes each, see memory maps for location, 8 bit access (narrow bus).
/WE Memory Write Enable signal, Active Low. Valid with ECLK high and R/W low.
IRQ HC12 IRQ (PE1) Interrupt Input.
/RW HC12 Read/Write (PE2) control signal.
EHC12 ECLK (PE4) bus clock signal. Stretch should be enabled in software.
/RESET HC12 active low RESET signal.
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